Semiconductor memory device with error correction

A semiconductor memory device comprising

• a first memory region including a plurality of memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations;
• a second memory region configured to temporarily store data read from the first memory region or configured to temporarily store data to be written to the first memory region;
• an error-correcting circuit configured to calculate an error bit count of the read data;
• a controller configured to perform a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group;
• a maximum value register configured to hold a maximum error bit count among error bit counts during a period from a certain refresh operation to a next refresh operation;
• and
• a flag register configured to store flags for the memory blocks, one of the flags indicating a first read operation to the corresponding memory block after restart of a supply of power to the first memory region, when the supply of the power restarts after stop thereof, wherein
• when the error bit count in the first read operation since the supply of the power to the first memory region restarts is higher than the maximum error bit count before the restart of the supply of the power, the controller executes the refresh operation.