Failsoft system for multiple CPU system
AssigneeSilicon Graphics, Inc.
InventorsPatrick John Donlin, Samuel Edward Watters
Life of this patent
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Abstract
A cpu-set type multiprocessor system allows a cpu of a cpu-set that has a hardware exception to disable itself and notify the system. The system assigns processes of the cpu-set that include the problem cpu to another cpu-set. The disabling of the problem cpu and transfer of the related processes to another cpu-set allows the system to failsoft so that other cpu-sets the multiprocessor system can continue to run and a recovery of the processes being run on the problem cpu-set occurs.
Claims18
A method of responding to errors in a high performance computing system that has a control processor executing an operating system, a plurality of computing processors for executing computational tasks within the operating system, and a memory that the control processor and the plurality of computing processors share, the method comprising:
- the operating system forming a first plurality of computing processors that cooperate to execute a first task within the operating system, and a second, non-overlapping plurality of computing processors that cooperate to execute a second task within the operating system, wherein the control processor is not assigned to the first or second plurality;
- determining, by a first computing processor in the first plurality, whether the first computing processor has encountered a problem;
- the operating system deactivating the first computing processor after the problem has occurred;
- and
- in response to the first computing processor determining that it has encountered the problem, the operating system using the shared memory to form a third plurality of computing processors that cooperate to continue executing the first task after the problem has occurred.
A high performance computing system comprising:
- a memory;
- a plurality of computing processors, each computing processor sharing access to the memory, each computing processor being configured to determine if the computing processor has encountered a problem;
- and
- a control processor sharing access to the memory with the plurality of computing processors, the control processor being configured to execute operating system processes that:
- (a) form non-overlapping first and second pluralities of computing processors, the first plurality of computing processors cooperating to execute a first computing task, the second plurality of computing processors cooperating to execute a second computing task;
- (b) deactivate a first computing processor in the first plurality after the first computing processor has determined that a problem has occurred;
- and
- (c) in response to the first computing processor determining that it has encountered the problem, use the shared memory to form a third plurality of computing processors that cooperate to continue executing the first task after the problem has occurred.
A computer program product for use in a high performance computing system that has a control processor executing an operating system, a plurality of computing processors for executing computational tasks within the operating system, and a memory that the control processor and the plurality of computing processors share, the computer program product comprising a non-transitory computer-readable storage having computer readable program code thereon, the computer readable program code comprising:
- program code for forming a first plurality of computing processors that cooperate to execute a first task within the operating system, and a second, non-overlapping plurality of computing processors that cooperate to execute a second task within the operating system, wherein the control processor is not assigned to the first or second plurality;
- program code for causing a first computing processor in the first plurality to determine whether the first computing processor has encountered a problem;
- program code for causing the operating system to deactivate the first computing processor after the problem has occurred;
- and
- program code for causing the operating system to respond to the first computing processor encountering the problem by using the shared memory to form a third plurality of computing processors that cooperate to continue executing the first task after the problem has occurred.
Dependencies are inferred from the claim text.