US 8,078,890 B2Granted

System and method for providing memory performance states in a computing system

AssigneeDell Products L.P.

InventorsVijay Nijhawan, Madhusudhan Rangarajan

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Abstract

A system and method is disclosed for providing memory performance states in a computing system. The operating system power management component of the computing system establishes a set of performance states, with each performance state being defined by a number of factors, including the core frequency of memory. The operating system power management component also defines the number of memory performance states that are supported by the computing system and the number of supported memory performance states that are available for use by the computing system. Whether a supported memory performance state is available is dependent upon a measure of the power being consumed by the computing system, the thermal output of the computing system, or both measures.

Claims19

Dependent claims

A computing system, comprising:

a processor;
memory;
an operating system, wherein:
the operating system includes a power management component that is operable to place the memory of the computer system in multiple memory performance states of operation,
the multiple memory performance states of operation differ from one another according to the amount of power consumed by memory in each state of operation,
the operating system includes a supported states routine that produces an output identifying the multiple memory performance states of operation supported by the computing system,
the operating system includes a capabilities routine that produces an output identifying a set of the multiple memory performance states of operation supported by the computing system that are available for use,
the operating system is operable to limit the memory to the set of multiple memory performance states identified by the output of the capabilities routine, and
the operating system is further operable to cause a transition from a first of the multiple memory performance states of operation to a second of the multiple memory performance states of operation, wherein if the transition from the first of the multiple memory performance states of operation to the second of the multiple memory performance states of operation is unsuccessful after a predetermined number of attempts, the operating system returns to the first of the multiple memory performance states of operation.

6 more elements

A method for transition between a first memory performance state and second memory performance state in a computing system, comprising:

writing a value to a control register, wherein the value is uniquely associated with the second performance state, wherein the second performance state is identified by the output of a supported states routine in the computing system as one of a plurality of memory performance states supported by the computing system, and wherein the second performance state is limited by a capabilities routine of the computing system to one of the plurality of memory performance states that are available for use;
writing a value to a status register, wherein the value is uniquely associated with a successful transition to the second memory performance state;
modifying the core frequency of the memory of the computing system to the predetermined core frequency associated with the second performance state;
running a test routine;
comparing the output of the test routine to the value of the status register to verify that the computing system successfully transitioned to the second memory performance state;
and
returning to the first memory performance state if the computing system does not successfully transition to the second memory performance state after the step of running the test routine is performed a predetermined number of times.

4 more elements

A method for transitioning between a first memory performance state and a second memory performance state in a computing system, comprising:

identifying the supported memory performance states in the computing system by an output of a supported states routine in the computing system;
identifying the available memory performance states among the supported memory performance states of the computing system by an output of a capabilities routine in the computing system;
writing a value to a control register, wherein the value is uniquely associated with the second performance state, wherein the second performance state is limited by the computing system to the available memory performance states identified by the output of the capabilities routine;
writing a value to a status register, wherein the value is uniquely associated with a successful transition to the second memory performance state;
modifying the core frequency of the memory of the computing system to the predetermined core frequency associated with the second performance state
running a test routine;
comparing the output of the test routine to the value of the status register to verify that the computing system successfully transitioned to the second memory performance state;
and
returning to the first memory performance state if the computing system does not successfully transition to the second memory performance state after the step of running the test routine is performed a predetermined number of times.

6 more elements

Dependencies are inferred from the claim text.