US 8,078,854 B2 · Using register rename maps to facilitate precise exception semantics

Abstract

One embodiment of the present invention provides a system that facilitates precise exception semantics. The system includes a processor that uses register rename maps to support out-of-order execution, where the register rename maps track mappings between native architectural registers and physical registers for a program executing on the processor. These register rename maps include: 1) a working rename map that maps architectural registers associated with a decoded instruction to corresponding physical registers; 2) a retire rename map that tracks and preserves a set of physical registers that are associated with retired instructions; and 3) a checkpoint rename map that stores a mapping between a set of architectural registers and a set of physical registers for a preceding checkpoint in the program. When the program signals an exception, the processor uses the checkpoint rename map to roll back program execution to the preceding checkpoint.

Claims18

Dependent claims

A computing device that uses register rename maps to facilitate precise exception semantics, comprising:

a processor that supports out-of-order execution, wherein the processor includes a plurality of register rename maps that track mappings between architectural registers and physical registers for a program executing on the processor;
wherein the plurality of register rename maps include:
a working rename map that maps architectural registers associated with a decoded instruction to corresponding physical registers;
a retire rename map that tracks and preserves a set of physical registers that are associated with retired instructions;
and
a checkpoint rename map that stores a mapping between a set of architectural registers and a set of physical registers for a preceding checkpoint in the program;
wherein when the program causes an exception, the processor is configured to use the checkpoint rename map to roll back program execution to the preceding checkpoint;
wherein the program executes in a virtual machine that is configured to deliver the exception at a precise virtual program counter and with a precise state defined by the instruction set architecture of the virtual machine.

5 more elements

A method for using register rename maps to facilitate precise exception semantics for a program, wherein the program executes on a processor that supports out-of-order execution, wherein the processor tracks mappings between architectural registers and physical registers for the program using a working rename map, a retire rename map, and a checkpoint rename map, the method comprising:

using the working rename map to map architectural registers associated with a decoded instruction to corresponding physical registers;
using the retire rename map to track and preserve a set of physical registers that are associated with retired instructions;
using the checkpoint rename map to store a mapping between a set of architectural registers and a set of physical registers for a preceding checkpoint in the program;
and
when the program causes an exception, using the checkpoint rename map to roll back program execution to the preceding checkpoint;
and
wherein the program executes in a virtual machine that is configured to deliver the exception at a precise virtual program counter and with a precise state defined by the instruction set architecture of the virtual machine.

4 more elements

Dependencies are inferred from the claim text.

Using register rename maps to facilitate precise exception semantics

Life of this patent

Using register rename maps to facilitate precise exception semantics

Life of this patent

Abstract

Claims18