Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated

A method for implementing a conditional move in a processor, comprising:

• forming a first decoded instruction and a second decoded instruction from a conditional move instruction comprising a first, second, and third operand, the third operand being both a source and a destination, wherein the first decoded instruction comprising the second and third operands from the conditional move instruction causes the processor to move the third operand to a completion buffer register if a first condition is satisfied, and the second decoded instruction comprising the first and second operands from the conditional move instruction causes the processor to move the first operand to the completion buffer register if the first condition is not satisfied;
• allocating a register in a completion buffer as a destination register to temporarily store any result of the first and second decoded instructions;
• executing the first decoded instruction and the second decoded instruction;
• graduating the second decoded instruction and invalidating the first decoded instruction if the first condition is not satisfied;
• graduating the first decoded instruction and invalidating the second decoded instruction if the first condition is satisfied.

A method for implementing in a processor a conditional move instruction that specifies a first operand, a second operand, and a third operand, the method comprising:

• forming a first decoded instruction comprising the second and third operands from the conditional move instruction and a second decoded instruction comprising the first and second operands from the conditional move instruction, wherein the first decoded instruction causes the processor to move the third operand to a completion buffer register if the second operand is not equal to a predetermined value, and the second decoded instruction causes the processor to move the first operand to the completion buffer register if the second operand is equal to the predetermined value;
• allocating a register in a completion buffer as a destination register to temporarily store any result of the first and second decoded instructions;
• if the second operand is equal to the predetermined value, graduating the second decoded instruction, thereby altering an architectural state of the processor according to the second decoded instruction, and invalidating the first decoded instruction;
• and
• if the second operand is not equal to the predetermined value, graduating the first decoded instruction, thereby altering the architectural state of the processor according to the first decoded instruction, and invalidating the second decoded instruction.

A method for implementing a conditional move instruction, comprising:

• receiving the conditional move instruction comprising a first, second, and third operand, the third operand being both a source and a destination;
• forming a first decoded instruction comprising the second and third operands from the conditional move instruction and a second decoded instruction comprising the first and second operands from the conditional move instruction;
• allocating a register in a completion buffer as a destination register to temporarily store any result of the first and second decoded instructions;
• executing the decoded instructions, and
• graduating one of the decoded instructions,
• wherein if a first condition is satisfied, the first decoded instruction is invalidated and the second decoded instruction is graduated such that the second decoded instruction causes the first operand to be moved to the allocated completion buffer register, and
• wherein if the first condition is not satisfied, the second decoded instruction is invalidated and the first decoded instruction is graduated such that the first decoded instruction causes the third operand to be moved to the allocated completion buffer register.

A processor that implements a conditional move instruction, comprising:

• an instruction decode and dispatch unit configured to receive the conditional move instruction comprising a first, second, and third operand, the third operand being both a source and a destination, to output, without stalling the instruction decode and dispatch unit, a first decoded instruction comprising the second and third operands from the conditional move instruction and a second decoded instruction comprising the first and second operands from the conditional move instruction, and to allocate a register in a completion buffer as a destination register to temporarily store any result of the first and second decoded instructions,
• wherein the first decoded instruction causes the processor to move the third operand to the completion buffer register if a first condition is satisfied, and the second decoded instruction causes the processor to move the first operand to the completion buffer register if the first condition is not satisfied,
• a hardware execution unit, coupled to the instruction decode and dispatch unit, configured to execute the first decoded instruction and the second decoded instruction and;
• a graduation unit configured to graduate either the first or the second decoded instructions,
• wherein, if the first condition is not satisfied, the second decoded instruction is graduated and the first decoded instruction is invalidated, and
• wherein, if the first condition is satisfied, the first decoded instruction is graduated and the second decoded instruction is invalidated.

A method for implementing a conditional move in a processor, comprising:

• forming a first decoded instruction and a second decoded instruction from a conditional move instruction comprising a first, second, and third operand, the third operand being both a source and a destination, without stalling a decode stage of the processor, wherein the first decoded instruction comprising the second and third operands from the conditional move instruction causes the processor to move the third operand to a completion buffer register if a first condition is satisfied, and the second decoded instruction comprising the first and second operands from the conditional move instruction causes the processor to move the first operand to the completion buffer register if the first condition is not satisfied;
• allocating a register in a completion buffer as a destination register to temporarily store any result of the first and second decoded instructions;
• executing the first decoded instruction and the second decoded instruction, and
• graduating one of the decoded instructions,
• wherein, if a first condition is satisfied, the second decoded instruction is invalidated and the first decoded instruction is graduated, and
• wherein, if a first condition is not satisfied, the first decoded instruction is invalidated and the second decoded instruction is graduated.

A processor that implements a conditional move instruction, comprising:

• an instruction decode and dispatch unit configured to receive the conditional move instruction comprising a first, second, and third operand, the third operand being both a source and a destination and to output a first decoded instruction comprising the second and third operands from the conditional move instruction and a second decoded instruction comprising the first and second operands from the conditional move instruction,
• wherein the first decoded instruction causes the processor to move the third operand to a completion buffer register if a first condition is satisfied, and the second decoded instruction causes the processor to move the first operand to the completion buffer register if the first condition is not satisfied,
• a hardware execution unit, coupled to the instruction decode and dispatch unit, configured to execute the first decoded instruction and the second decoded instruction, and;
• a graduation unit configured to graduate either the first or the second decoded instruction,
• wherein, if the first condition is not satisfied, the second decoded instruction is graduated and the first decoded instruction is invalidated, and
• wherein, if the first condition is satisfied, the first decoded instruction is graduated and the second decoded instruction is invalidated.

A processor that implements a conditional move instruction, comprising:

• an instruction decode and dispatch unit configured to receive the conditional move instruction that specifies a first source operand, a second source operand, and a third source operand that is both a source and a destination, and to output a first decoded instruction and a second decoded instruction;
• a hardware execution unit, coupled to the instruction decode and dispatch unit, configured to execute the first decoded instruction and the second decoded instruction;
• and
• a graduation unit configured to graduate either the first or the second decoded instruction,
• wherein, if a first condition is not satisfied, the first decoded instruction is invalidated and the second decoded instruction is graduated such that the second decoded instruction causes the first source operand to be moved to an allocated completion buffer register, and
• wherein, if the first condition is satisfied, the second decoded instruction is invalidated and the first decoded instruction is graduated such that the first decoded instruction causes the third source operand to be moved to the allocated completion buffer register.