Device and method for processing instructions based on masked register group size information

A method for processing instructions, the method comprises:

• receiving a second instruction and initializing a pipelined execution process of the second instruction;
• receiving a first instruction and initializing a pipelined execution process of the first instruction;
• providing to a controller a second register group size information and a second register identification information that define a second group of target registers associated with the second instruction;
• providing to the controller a first register group size information and a first register identification information that define a first group of source registers associated with the first instruction;
• masking, by the controller, the first register identification information, wherein a total number of least significant bits masked in the masked first register identification information is less than a total number of source registers associated with the first instruction;
• determining, by the controller, an execution related operation of the first instruction in response to the first register group size information, the masked first register identification information, the second register group size information and the second register identification information;
• and
• performing the execution related operation;
• wherein the pipelined execution process of the first instruction comprises the execution related operation.

A device comprising:

• a pipelined processor;
• an instruction memory unit;
• and
• a register file;
• wherein the pipelined processor comprises:
• a write-back unit;
• and
• an execution unit;
• a controller that is adapted to receive a first register group size information and a first register identification information that define a first group of source registers associated with a first instruction, and to determine an execution related operation of the first instruction in response to the first register group size information, the first register identification information, a second register group size information and a second register identification information, and the controller is adapted to mask the first register identification information by the first register group size to provide a first masked instruction register identifier, to mask the second register identification information by the second register group size to provide a second masked instruction register identifier, and to compare between the second masked instruction register identifier and the first masked instruction register identifier, wherein a total number of least significant bits masked in the first masked instruction register identifier is less than a total number of source registers associated with the first instruction, and a total number of least significant bits masked in the second masked instruction register identifier is less than a total number of target registers associated with the second instruction;
• wherein the second register group size information and the second register identification information define a second group of target registers associated with a second instruction;
• and
• wherein the second instruction is provided to the pipelined processor before the first instruction.