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US 8,078,842 B2Granted
Removing local RAM size limitations when executing software code
AssigneeTexas Instruments Incorporated
InventorsGilbert Cabillic, Gerard Chauvel, Jean-Philippe Lesot
Life of this patent
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Abstract
An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory externally coupled to the processor, as well as a second group of instructions. When executed, the first group of instructions causes the processor to execute the second group of instructions in lieu of the individual instruction.
Claims16
An electronic device, comprising:
- a processor configured to directly execute at least some bytecodes in an instruction set of the processor, the processor comprising:
- decode logic;
- a vector table comprising a plurality of entries, wherein each entry of the plurality of entries corresponds to a bytecode in the instruction set and each entry comprises:
- a first field for indicating whether a micro-sequence is to be executed instead of the corresponding bytecode;
- and
- a second field for storing a reference to the micro-sequence;
- and
- an instruction memory configured to store micro-sequences referenced by the entries in the vector table;
- and
- a memory externally coupled to the processor, wherein the memory is configured to store a group of instructions that is to be executed instead of a bytecode,
- wherein the decode logic is configured to:
- use a bytecode to locate an entry of the vector table corresponding to the bytecode;
- and
- cause a micro-sequence referenced in the second field of the entry to be executed when the first field of the entry indicates that a micro-sequence is to be executed instead of the bytecode,
- wherein, when executed, the micro-sequence causes the processor to execute the group of instructions.
12 more elements
A processor configured to directly execute at least some bytecodes in an instruction set of the processor, the processor comprising:
- decode logic;
- a vector table comprising a plurality of entries, wherein each entry of the plurality of entries corresponds to a bytecode in the instruction set and each entry comprises:
- a first field for indicating whether a micro-sequence is to be executed instead of the corresponding bytecode;
- and
- a second field for storing a reference to the micro-sequence;
- and
- an instruction memory configured to store micro-sequences referenced by the entries in the vector table,
- wherein the decode logic is configured to:
- use a bytecode to locate an entry of the vector table corresponding to the bytecode;
- and
- cause a micro-sequence referenced in the second field of the entry to be executed when the first field of the entry indicates that a micro-sequence is to be executed instead of the bytecode,
- wherein, when executed, the micro-sequence causes the processor to execute a group of instructions stored in a memory external to the processor, and
- wherein execution of the micro-sequence causes the decode logic to push onto a stack data pertaining to a state of the processor.
10 more elements
A method comprising:
- using a bytecode to locate an entry corresponding to the bytecode in a vector table, wherein the vector table comprises an entry for each bytecode in an instruction set of a processor;
- causing a micro-sequence referenced in a second field of the entry to be executed when a first field in the entry indicates that the micro-sequence is to be executed by the processor instead of executing the bytecode,
- wherein the micro-sequence is stored in an instruction memory comprised in the processor,
- wherein, when executed, the micro-sequence causes the processor to execute a group of instructions stored in a memory external to the processor, and
- wherein execution of the micro-sequence causes registers pertaining to a state of the processor to be pushed onto a stack before the group of instructions is executed.
2 more elements
Dependencies are inferred from the claim text.