US 8,078,839 B2 · Concurrent processing element system, and method

Abstract

An electronic processing element is disclosed for use in a system having a plurality of processing elements. The electronic processing element includes an input instruction memory, an operation unit, and an output instruction memory. The input instruction memory is configured to store and retrieve a plurality of operation codes and, for each operation code, an associated output instruction memory address. The operation unit is configured to generate an output datum defined by at least a selected operation code and an associated input datum. The output instruction memory is configured to receive the output instruction memory address and to retrieve an address for an input instruction memory of a second processing element. Upon selection of an input instruction memory address and presentation of an associated input datum, the processing element generates an output datum in association with a corresponding input instruction memory address of the second processing element.

Claims20

Dependent claims

An electronic processing element for use in a system having a plurality of processing elements, a first processing element of the plurality of processing elements comprising:

(a) an input instruction memory configured to store and output a plurality of operation codes and, for each operation code, store and output an associated output instruction memory address;
(b) an operation unit configured to generate an output datum defined by at least a selected operation code and an associated input datum;
and
(c) an output instruction memory configured to receive the output instruction memory address and to output an address for an input instruction memory of a second processing element;
whereby, upon receipt of an input instruction memory address and of an associated input datum, the processing element generates an output datum in association with a corresponding input instruction memory address of the second processing element.

2 more elements

A method using a plurality of electronic processing elements to perform a process expressed as a set of predetermined instructions, said method comprising:

(a) providing a plurality of processing units, each processing unit including
(i) an operation unit configured to generate an output datum in response to at least one input datum and an operation code, and
(ii) an instruction memory configured to store and output instructions, said instruction memory including
(A) an input instruction memory configured to store and output an operation code and a memory address for an output instruction memory, and
(B) an output instruction memory configured to store and output at least one memory address for a subsequent instruction of the process;
(b) storing instructions in instruction memories such that
(i) an instruction memory associated with a first processing element stores a first instruction that produces a datum,
(ii) an instruction memory associated with a second processing element stores a second instruction that operates on the datum, and
(iii) the first instruction includes an address for the second instruction;
and
(c) performing the process by
(i) associating data with input memory instruction addresses for instructions to process the data, and
(ii) communicating associated data and input memory instruction addresses together among processing elements.

10 more elements

An electronic method using a plurality of processing elements to perform at least two processes concurrently, said first process expressed as a first set of predetermined instructions and said second process expressed as a second set of predetermined instructions, said method comprising:

(a) providing a plurality of processing units, each processing unit including
(i) an operation unit configured to generate an output datum in response to at least one input datum and an operation code, and
(ii) an instruction memory configured to store and output instructions, said instruction memory including
(A) an input instruction memory configured to store and output an operation code and a memory address for an output instruction memory, and
(B) an output instruction memory configured to store and output at least one memory address for a subsequent instruction of a process;
(b) storing the first set of instructions in instruction memories such that
(i) an instruction memory associated with a first processing element stores a first instruction of the first set of instructions that produces a first datum,
(ii) an instruction memory associated with a second processing element stores a second instruction of the first set of instructions to process the first datum, and
(iii) the first instruction of the first set of instructions includes an address for the second instruction of the first set;
(c) storing the second set of instructions in instruction memories such that
(i) an instruction memory associated with a first processing element stores a first instruction of the second set of instructions that produces a second datum,
(ii) an instruction memory associated with a third processing element stores a second instruction of the second set of instructions to process the second datum, and
(iii) the first instruction of the second set of instructions includes an address for the second instruction of the second set;
and
(d) performing the processes concurrently by, for both process
(i) associating data with input memory instruction addresses for instructions operating on the data, and
(ii) communicating associated data and input memory instruction addresses together among processing elements.

14 more elements

Dependencies are inferred from the claim text.

Concurrent processing element system, and method

Life of this patent

Concurrent processing element system, and method

Life of this patent

Abstract

Claims20