Reconfigurable array processor for floating-point operations

A reconfigurable array processor comprising:

• an array of processing elements configured to perform one or more floating-point operations,
• each of the processing elements comprising an arithmetic logic unit to receive and process two input values, and the processing elements in the array being connected together in groups of two or more processing elements, and being connected in a mesh structure to enable data communications among the processing elements,
• wherein the array is selectively configured to:
• perform an integer arithmetic operation using each of the processing elements;
• or
• perform the one or more floating-point operations using each of the groups of two or more processing elements;
• a configuration cache connected to the array to store a context configured to
• control one or more arithmetic operations performed by the processing elements in each column or row of the PE array, and
• enable data communications among the processing element,
• the processing elements being configured in columns or rows based on the context to form a pipeline, and a result of a pipeline operation being forwarded to a direction designated by the context;
• and
• a frame buffer connected to the array that operates as a cache memory to store an interim result of the one or more arithmetic operations performed by the array,
• wherein each of the groups of two or more processing units is configured to
• perform the integer arithmetic operation or the one or more floating-point arithmetic operations through temporal mapping;
• receive the context of a control signal so as to perform a multi-cycle operation;
• and
• receive a next context after final values through all cycles are obtained.

A computing platform comprising:

• a reconfigurable array processor comprising a plurality of components including:
• an array of processing elements configured to perform an integer arithmetic operation using each of the processing elements, or perform one or more floating-point operations using each of the two or more groups of two or more processing elements connected together,
• wherein each of the processing elements comprises an arithmetic logic unit to receive and process two input values;
• and
• the processing elements of the array are connected in a mesh structure to enable data communications among the processing elements;
• a configuration cache connected to the array to store a context configured to
• control one or more arithmetic operations performed by the processing elements in each column or row of the PE array, and
• enable data communications among the processing element,
• wherein the processing elements are configured in columns or rows based on the context to form a pipeline, and a result of a pipeline operation is forwarded to a direction designated by the context;
• and
• a frame buffer connected to the array that operates as a cache memory to store an interim result of the one or more arithmetic operations performed by the array;
• a system bus connected to the reconfigurable array processor;
• and
• a control and memory unit connected to the reconfigurable array processor through the system bus to control the reconfigurable array processor and store data,
• wherein each of the groups of two or more processing units is configured to
• perform the integer arithmetic operation or the one or more floating-point arithmetic operations through temporal mapping;
• receive the context of a control signal so as to perform a multi-cycle operation;
• and
• receive a next context after final values through all cycles are obtained.

A method of performing at least one of an integer arithmetic operation and a floating-point operation by temporal mapping with an array of processing elements comprising:

• receive a context stored in a configuration cache so as to perform a multi-cycle operation;
• and
• receive a next context after final values through all cycles are obtained,
• wherein the processing elements in the array are connected together in groups of two or more processing elements to enable floating-point operation, and are connected in a mesh structure to enable data communications among the connected processing elements,
• wherein the processing elements are configured in columns or rows based on the context to form a pipeline, and a result of a pipeline operation being forwarded to a direction designated by the context.