Processor architectures for enhanced computational capability
AssigneeAnalog Devices, Inc.
InventorDouglas Garde
Life of this patent
Estimating the term…
Abstract
A digital signal processor includes a control block configured to issue instructions based on a stored program, and a compute array including two or more compute engines configured such that each of the issued instructions executes in successive compute engines of at least a subset of the compute engines at successive times. The digital signal processor may be utilized with a control processor or as a stand-alone processor. The compute array may be configured such that each of the issued instructions flows through successive compute engines of at least a subset of the compute engines at successive times.
Claims48
A digital signal processor comprising:
- a control block configured to issue flow instructions and flow data based on a stored program;
- and
- a compute array including plurality of serially connected compute engines configured such that (i) each of the issued flow instructions executes in a first compute engine and flows, in a single direction, to be executed in each successive compute engine of the plurality of serially connected compute engines at successive times, and (ii) the flow data recirculates from a last compute engine in the plurality of serially connected compute engines directly back to the first compute engine.
A method for digital signal processing comprising:
- providing a digital signal processor comprising a control block and a compute array including a plurality of serially connected compute engines;
- issuing flow instructions and flow data in the control block based on a stored program;
- executing each of the issued flow instructions in a first compute engine;
- circulating each of the issued flow directions in a single direction to, and executing each of the issued flow directions in, each successive compute engine of the plurality of serially connected compute engines at successive times;
- and
- recirculating the flow data from a last compute engine in the plurality of serially connected compute engines directly back to the first compute engine.
A digital signal processor comprising:
- a control processor;
- a processor comprising a control block configured to issue flow instructions and flow data based on a stored program, and a compute array including a plurality of serially connected compute engines configured such that (i) each of the issued flow instructions executes in a first compute engine and flows, in a single direction, to be executed in each successive compute engine of the plurality of serially connected compute engines at successive times, and (ii) the flow data recirculates from a last compute engine in the plurality of serially connected compute engines directly back to the first compute engine;
- and
- a main memory that can be accessed by the control processor and by the processor.
Dependencies are inferred from the claim text.