Virtual architectures in a parallel processing environment
AssigneeMassachusetts Institute of Technology
InventorsAnant Agarwal, David Wentzlaff
Life of this patent
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Abstract
An integrated circuit includes a plurality of processor core. Processing instructions in the integrated circuit includes: managing a plurality of sets of processor cores, each set including one or more processor cores assigned to a function associated with executing instructions; and reconfiguring the number of processor cores assigned to at least one of the sets during execution based on characteristics associated with executing the instructions.
Claims23
A method for processing instructions in an integrated circuit, the integrated circuit comprising a plurality of processor cores, the method comprising:
- assigning blocks of instructions to a set of one or more processor cores to translate the instructions into translated instructions, the blocks of instructions being associated with an execution order;
- determining whether a first translated instruction is stored in a cache accessible to an execution processor core, and sending a request from the execution processor core to at least one processor core in the set to translate one or more instructions to generate the first translated instruction if the first translated instruction is not stored in the cache;
- and
- executing in the execution processor core the first translated instruction while the set of one or more processor cores are translating instructions that occur later in the execution order than the first translated instruction.
An integrated circuit, comprising:
- at least one processor core configured to assign blocks of instructions to a set of one or more processor cores to translate the instructions into translated instructions, the blocks of instructions being associated with an execution order;
- an execution processor core configured to determine whether a first translated instruction is stored in a cache accessible to the execution processor core, and configured to send a request to at least one processor core in the set to translate one or more instructions to generate the first translated instruction if the first translated instruction is not stored in the cache;
- the execution processor core configured to execute the first translated instruction while the set of one or more processor cores are translating instructions that occur later in the execution order than the first translated instruction.
Dependencies are inferred from the claim text.