US 8,078,831 B2 · Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors

Abstract

Apparatus, system and methods are provided for performing speculative data prefetching in a chip multiprocessor (CMP). Data is prefetched by a helper thread that runs on one core of the CMP while a main program runs concurrently on another core of the CMP. Data prefetched by the helper thread is provided to the helper core. For one embodiment, the data prefetched by the helper thread is pushed to the main core. It may or may not be provided to the helper core as well. A push of prefetched data to the main core may occur during a broadcast of the data to all cores of an affinity group. For at least one other embodiment, the data prefetched by a helper thread is provided, upon request from the main core, to the main core from the helper core's local cache.

Claims8

Dependent claims

An apparatus comprising:

an integrated circuit including:
decode logic adapted to decode a trigger instruction from a main thread instruction stream into a decoded trigger instruction;
a first processor core adapted to execute the main thread instruction stream;
a first private cache coupled to the first processor core, the first private cache being adapted to be private to the first processor core;
a second processor core adapted to execute a helper thread instruction stream in response to the first processor core executing the decoded trigger instruction from the main thread;
a second private cache coupled to the second processor core, the second private cache being adapted to be private to the second processor core;
and
control logic adapted to prefetch data into the first private cache coupled to the first processor core in response to the second processor core executing the helper thread instruction stream.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

12/909,774Filed 21 Oct 2010 · continuation

Priority

31 Jul 2003

Published

US 2011/0035555 A110 Feb 2011

Granted

13 Dec 2011

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 9/3842
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: speculative instruction execution
G06F 9/383
Operand accessing: operand prefetching
G06F 9/3851
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: from multiple instruction streams, e.g. multistreaming
G06F 12/0862
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: with prefetch

Family

Application10/632,431Parent of this continuation · filed 31 Jul 2003

US 2011/0035555 A1Pre-grant publication · published 10 Feb 2011

US 7,844,801 B2Parent of this continuation

US 2005/0027941 A1Published application

US 8,078,831 B2This patent

From the US filing history. Foreign family members aren’t listed.

Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors

Life of this patent

Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors

Life of this patent

Abstract

Claims8