Scaleable array of micro-engines for waveform processing
AssigneeITT Manufacturing Enterprises, Inc.
InventorPatrick Arthur McCabe
Life of this patent
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Abstract
A system for implementing waveform processing in a software defined radio (SDR) includes a scaleable array processor having a plurality of micro-engines (MEs) interconnected by a two dimensional topology. Each micro-engine includes multiple FIFOs for interconnecting to each other in the two dimensional topology. One micro-engine communicates with another adjacent micro-engine by way of the respective FIFOs. The micro-engines are dedicated to predetermined algorithms. The two dimensional topology includes an array of N×M micro-engines interconnected by the multiple FIFOs. The N×M are integer numbers of rows and columns, respectively, in the array of micro-engines. The micro-engines are dedicated to baseband processing of data for RF transmission or RF reception.
Claims10
A system for implementing waveform processing in a software defined radio (SDR) comprising
- a scaleable array processor including a plurality of micro-engines interconnected by a two dimensional topology,
- each micro-engine including multiple FIFOs for interconnecting to each other in the two dimensional topology,
- one micro-engine communicating with another adjacent micro-engine by way of the respective FIFOs, and
- the micro-engines dedicated to predetermined algorithms;
- wherein
- each micro-engine includes an independent local memory and an independent instruction memory, both coupled to an independent microprocessor, and
- the independent microprocessor is configured to execute an independent algorithm on data present in a dedicated FIFO of the respective micro-engine,
- each micro-engine is event driven, wherein unless data is present in an input FIFO of the respective micro-engine, the respective micro-engine is in a sleep mode, and
- the sleep mode disables a clock signal controlling the independent microprocessor and stops the execution of the independent algorithm, if all the multiple FIFOs of a respective micro-engine are empty, and the clock signal is generated by a phase locked loop;
- and
- wherein each processing engine includes a plurality of registers for executing multiple independent instructions,
- the plurality of registers from each processing engine are coupled to a multiplexer network, and
- a debug port is coupled between the multiplexer network and a host processor, and the host processor is configured to query each of the plurality of registers and receive data stored in the queried register by way of the multiplexer network for debug examination.
An array processing system comprising
- a plurality of processing engines interconnected as an array processor,
- each processing engine including multiple FIFOs,
- at least one FIFO of the multiple FIFOs of each processing engine providing an interconnection to at least another FIFO of the multiple FIFOs of another processing engine,
- each processing engine having an independent local memory,
- each processing engine having an independent instruction memory coupled to an independent microprocessor for executing multiple independent instructions,
- each processing engine including a plurality of registers for executing the multiple independent instructions,
- the plurality of registers from each processing engine coupled to a multiplexer network,
- a debug port coupled between the multiplexer network and a host processor,
- wherein the host processor is configured to query each of the plurality of registers and receive data stored in the queried register by way of the multiplexer network for debug examination,
- the processing engines, the multiplexer network, and the debug port of each processing engine are integrated on a single system on a chip (SOC), and
- a clock signal generated by a phase locked loop,
- wherein
- each of the processing engines is event driven, wherein unless data is present in an input FIFO of the respective processing engine, the respective processing engine is in a sleep mode, and
- the sleep mode disables the clock signal controlling a respective processing engine and stops the execution of the multiple independent instructions, if all the multiple FIFOs of the respective processing engine are empty.
Dependencies are inferred from the claim text.