Microprocessor with improved data stream prefetching

A method for prefetching a data stream into a microprocessor from a system memory coupled to the microprocessor, the microprocessor having a translation look-aside buffer (TLB), the method comprising:

• decoding an instruction, specifying the data stream, a fetch-ahead distance, and a parameter specifying an abnormal TLB access policy;
• monitoring load requests generated by the microprocessor to determine if one of said load requests hits in the data stream within said fetch-ahead distance of a last prefetch from the data stream;
• generating a prefetch request to prefetch a cache line of said data stream from the system memory into the microprocessor in response to said monitoring, said new request including a virtual page address of said cache line;
• and
• selectively aborting said prefetch request if said virtual page address causes an abnormal access of said TLB, based on said abnormal TLB access policy specified in said parameter.

A computer readable storage medium, having thereon computer readable program code to generate a processor, the computer readable program code comprising:

• first program code for providing a memory subsystem, having a translation look-aside buffer (TLB) for storing TLB information;
• second program code for providing an instruction decode unit, coupled to said memory subsystem, for decoding an instruction, said instruction specifying a data stream in the system memory and an abnormal TLB access policy;
• and
• third program code for providing a stream prefetch unit, coupled to said memory subsystem, for generating a prefetch request to said memory subsystem to prefetch a cache line of said data stream from the system memory into said memory subsystem, wherein if a virtual page address of said prefetch request causes an abnormal TLB access, said memory subsystem selectively aborts said prefetch request based on said abnormal TLB access policy specified in said instruction.