Method and arrangement for cache memory management, related processor architecture
AssigneeSTMicroelectronics S.r.l.
InventorsFrancesco Pappalardo, Giuseppe Notarangelo, Elena Salurso, Elio Guidetti
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Abstract
A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in a scalar mode or in a vectorial mode. This is done by explicitly mapping the data locations that are scalar and the data locations that are vectorial.
Claims12
A method for managing a data cache memory associated with a processor comprising a plurality of processor clusters that operate simultaneously on scalar and vectorial data, the plurality of processor clusters comprising a low cluster and a high cluster coupled to the data cache memory via an intercluster data path, with the low cluster being selectably activated to only operate on the scalar data and with both the low and high clusters being selectably activated to operate on the vectorial data, the method comprising:
- providing in the data cache memory data locations for storing therein data for processing by the plurality of processor clusters;
- and
- accessing the data locations in the data cache memory via the intercluster data path either in a scalar mode or in a vectorial mode, each processor cluster comprising a plurality of processing elements, with the plurality of processing elements in each processor cluster being symmetrical with the plurality of processing elements in other processor clusters so that activating the low cluster only supports the scalar mode and activating both the the low cluster along with the high cluster supports the vectorial mode, with the accessing based on the following
- if accessing the data locations is in the scalar mode, then an address to be accessed is computed by the processor cluster that needs the data, and
- if accessing the data locations is in the vectorial mode, then the address to be accessed is computed by one of the processor clusters and is identical for all of them.
A processor comprising:
- a data cache memory for storing data for processing, with data locations therein being accessible either in a scalar mode or in a vectorial mode;
- an intercluster data path coupled to said data cache memory;
- and
- a plurality of processor clusters comprising a low cluster and a high cluster coupled to said intercluster data path and being selectably activated to operate on scalar and vectorial data, and for accessing the data locations via the intercluster data path either in the scalar mode or in the vectorial mode, each processor cluster comprising a plurality of processing elements, with the plurality of processing elements in each processor cluster being symmetrical with the plurality of processing elements in other processor clusters so that activating the low cluster only supports the scalar mode and activating both the low cluster along with the high cluster supports the vectorial mode, with the accessing based on the following
- if accessing the data locations is in the scalar mode, then an address to be accessed is computed based on its own data by the processor cluster that needs the data, and
- if accessing the data locations is in the vectorial mode, then the address to be accessed is computed only by one of the processor clusters and is identical for all of them.
A data cache memory associated with a processor comprising a plurality of processor clusters comprising a low cluster and a high cluster and being selectably activated to operate on scalar and vectorial data, the plurality of processor clusters being coupled to the data cache memory via an intercluster data path, the data cache memory comprising:
- data locations for storing data for processing by the plurality of processor clusters, with the data locations being accessible via the intercluster data path either in a scalar mode or in a vectorial mode, each processor cluster comprising a plurality of processing elements, with the plurality of processing elements in each processor cluster being symmetrical with the plurality of processing elements in other processor clusters so that activating the low cluster only supports the scalar mode and activating both the low cluster along with the high cluster supports the vectorial mode, with the accessing based on the following
- if accessing the data locations is in the scalar mode, then an address to be accessed is computed based on its own data by the processor cluster that needs the data, and
- if accessing the data locations is in the vectorial mode, then the address to be accessed is computed only by one of the processor clusters and is identical for all of them.
Dependencies are inferred from the claim text.