Apparatus and methods to reduce castouts in a multi-level cache hierarchy
AssigneeQUALCOMM Incorporated
InventorsThomas Philip Speier, James Norris Dieffenderfer, Thomas Andrew Sartorius
Life of this patent
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Abstract
Techniques and methods are used to control allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are controlled. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information.
Claims29
A tracking method to reduce allocation of displaced cache lines, the tracking method comprising:
- accessing a selected line to be displaced in a lower level cache in response to a memory access having a fetch address hit in a next higher level cache;
- identifying information associated with the selected line which indicates that the selected line is not present in the next higher level cache;
- and
- allocating, for the memory access having the fetch address hit in the next higher level cache, the selected line in the next higher level cache in response to the identified information and an allocation indication associated with a cache line in the lower level cache, wherein the allocation indication signifies the cache line is present in the next higher level cache.
A method to reduce castouts, the method comprising:
- accessing a selected line to be displaced in a level X cache in response to a memory access having a fetch address hit in a level X+1 cache;
- allocating, for the access having the fetch address hit in the level X+1 cache, the selected line in the level X+1 cache in response to an allocation bit of the selected line indicating the selected line is not present in the level X+1 cache and a cache line and an allocation bit associated with the cache line in the level X cache, wherein the allocation bit associated with the cache line allocated in the level X cache signifies the cache line is present in the level X+1 cache.
A memory system having a plurality of cache levels comprising:
- a lower level cache configured to store a plurality of first cache lines each with an allocation bit, each allocation bit indicating whether one of the plurality of first cache lines associated with the allocation bit was allocated in a next higher level cache;
- and
- a castout logic circuit configured to determine whether a first cache line selected for displacement from the plurality of first cache lines is a cache line that is redundant with a cache line in the next higher level cache based on an allocation bit associated with the selected first cache line in response to a memory access having a fetch address hit in the next higher level cache, to avoid a castout of the selected first cache line to the next higher level cache in response to the allocation bit of the selected first cache line that indicates the selected first cache line is redundant with a cache line in the next higher level cache, and to castout the selected first cache line to the next higher level cache, based on the allocation bit indicating the selected first cache line is not present in the next higher level cache for the access having the fetch address hit in the next higher level cache, wherein a cache line and an associated allocation bit are stored in the lower level cache for the access having the fetch address hit in the next higher level cache, the associated allocation bit signifies the cache line is present in the next higher level cache.
A tracking method to reduce allocation of displaced cache lines, the tracking method comprising:
- accessing a selected line to be displaced in a lower level cache in response to a memory access having a fetch address hit in a next higher level cache;
- identifying information associated with the selected line which indicates that the selected line is not present in the next higher level cache;
- and
- allocating, for the memory access having the fetch address hit in the next higher level cache, the selected line in response to the identified information at an address in the next higher level cache determined by a least recently used replacement policy of the next higher level cache.
Dependencies are inferred from the claim text.