Separate page table base address for minivisor
AssigneeAdvanced Micro Devices, Inc.
InventorsBenjamin C. Serebrin, Michael J. Haertel
Life of this patent
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Abstract
In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM)). The alternate address space may be the guest address space. An instruction in the minivisor/VMM may specify the alternate address space for a data access, permitting the minivisor/VMM to read guest memory state via the alternate address space. In another embodiment, a processor may implement a page table base address register dedicated for the minivisor's use. In still another embodiment, the minivisor may be implemented as a specified entry point in the VMM address space.
Claims20
A processor comprising:
- a first page table base address register configured to store a first page table base address locating one or more first page tables in memory;
- a second page table base address register configured to store a second page table base address locating one or more second page tables in memory;
- and
- an execution core coupled to the first page table base address register and the second page table base address register, wherein the execution core is configured to use the one or more first page tables to translate addresses during execution of a guest, and wherein the execution core is configured to use the one or more second page tables to translate addresses during execution of a minivisor, wherein the second page table base address register is dedicated to locating the one or more second page tables for the minivisor, and wherein the minivisor is executed responsive to a first guest exit mechanism that saves a first amount of guest state, and wherein a second guest exit mechanism stores a second amount of guest state that is greater than the first amount.
A method comprising:
- loading a first page table base address into a first page table base address register in a processor to locate one or more guest page tables in memory;
- loading a second page table base address into a second page table base address register in the processor to locate one or more minivisor page tables in memory, wherein the second page table base address register is dedicated to a minivisor;
- during execution of the guest, translating addresses generated by the guest using the one or more guest page tables responsive to the first page table base address in the first page table base address register;
- exiting to a minivisor using a first guest exit mechanism, the first guest exit mechanism saving a first amount of guest state, wherein a second guest exit mechanism stores a second amount of guest state that is greater than the first amount;
- and
- during execution of the minivisor, translating addresses generated by the minivisor using the one or more minivisor page tables responsive to the second page table base address in the second page table base address register.
A computer accessible storage medium storing a plurality of instructions which, when executed:
- cause a first page table base address to be loaded into a first page table base address register to locate one or more guest page tables in memory;
- cause a second page table base address to be loaded into a second page table base address register to locate one or more minivisor page tables in memory, wherein the second page table base address register is dedicated to a minivisor;
- wherein, during execution of the guest, addresses generated by the guest are translated using the one or more guest page tables responsive to the first page table base address in the first page table base address register, and wherein, during execution of the minivisor, addresses generated by the minivisor are translated using the one or more minivisor page tables responsive to the second page table base address in the second page table base address register, and wherein an exit from the guest to the minivisor is performed using a first guest exit mechanism, the first guest exit mechanism saving a first amount of guest state, wherein a second guest exit mechanism stores a second amount of guest state that is greater than the first amount.
Dependencies are inferred from the claim text.