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US 8,078,790 B1Granted
Fast unaligned cache access system and method
AssigneeInfineon Technologies AG
InventorKlaus J. Oberlaender
Life of this patent
Estimating the term…
Abstract
A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the cache lines are split among the towers, unaligned cache access can be performed. Furthermore, power can be conserved because not all the memory towers of the cache unit needs to be activated during some memory access operations.
Claims26
A cache unit comprising:
- a first memory tower, having a first way sub-tower and a second way sub-tower;
- a second memory tower, having a first way sub-tower and a second way sub-tower;
- a first cache line of the cache unit comprised of sequential data segments;
- wherein the first way sub-tower of the first memory tower includes a first plurality of non-sequential data segments of the first cache line and the first way sub-tower of the second memory tower includes a second plurality of non-sequential data segments of the first cache line.
1 more element
A method of operating a cache unit having a first memory tower and a second memory tower, the method comprising:
- storing a first plurality of non-sequential data segments of a first cache line in a first way sub-tower of the first memory tower;
- storing a second plurality of non-sequential data segments of the first cache line in a first way sub-tower of the second memory tower;
- storing a first plurality of non-sequential data segments of a second cache line in a second way sub-tower of the first memory tower;
- and
- storing a second plurality of non-sequential data segments of the second cache line in a second way sub-tower of the second memory tower.
2 more elements
A cache unit having a first memory tower and a second memory tower, comprising:
- means for storing a first plurality of non-sequential data segments of a first cache line in a first way sub-tower of the first memory tower;
- means for storing a second plurality of non-sequential data segments of the first cache line in a first way sub-tower of the second memory tower;
- means for storing a first plurality of non-sequential data segments of a second cache line in a second way sub-tower of the first memory tower;
- and
- means for storing a second plurality of non-sequential data segments of the second cache line in a second way sub-tower of the second memory tower.
2 more elements
A cache unit comprising:
- a first memory tower, having a first way sub-tower and a second way sub-tower;
- a second memory tower, having a first way sub-tower and a second way sub-tower;
- a first way multiplexer having a first input port coupled to the first way sub-tower of the first memory tower, a second input port coupled to the first way sub-tower of the first memory port, and an output port;
- and
- a data aligner coupled to the output port of the first way multiplexer and the output port of the second way multiplexer,
- wherein a first cache line of the cache unit includes a first plurality of data segments in the first way sub-tower of the first memory tower and a second plurality of data segments in the first way sub-tower of the second memory tower.
3 more elements
A method of operating a cache unit having a first memory tower and a second memory tower, the method comprising:
- storing a first plurality of data segments of a first cache line in a first way sub-tower of the first memory tower;
- storing a second plurality of data segments of the first cache line in a first way sub-tower of the second memory tower;
- storing a first plurality of data segments of a second cache line in a second way sub-tower of the first memory tower;
- storing a second plurality of data segments of the second cache line in a second way sub-tower of the second memory tower;
- activating a first physical line of the first memory tower, wherein the first physical line includes data segments from the first cache line and the second cache line;
- and
- activating a second physical line of the second memory tower, wherein the second physical line of the second memory tower includes data segments from the first cache line and the second cache line,
- wherein the first physical line of the first memory tower has a different address than the second physical line of the second memory tower.
5 more elements
A cache unit having a first memory tower and a second memory tower, comprising:
- means for storing a first plurality of data segments of a first cache line in a first way sub-tower of the first memory tower;
- means for storing a second plurality of data segments of the first cache line in a first way sub-tower of the second memory tower;
- means for storing a first plurality of data segments of a second cache line in a second way sub-tower of the first memory tower;
- means for storing a second plurality of data segments of the second cache line in a second way sub-tower of the second memory tower;
- means for activating a first physical line of the first memory tower, wherein the first physical line includes data segments from the first cache line and the second cache line;
- and
- means for activating a second physical line of the second memory tower, wherein the second physical line of the second memory tower includes data segments from the first cache line and the second cache line,
- wherein the first physical line of the first memory tower has a different address than the second physical line of the second memory tower.
5 more elements
Dependencies are inferred from the claim text.