US 8,078,784 B2 · Method and apparatus for data movement in a system on a chip

Abstract

There is provided a system for comprising a plurality of blocks, each block comprising any hardware element and a plurality of segments for providing interconnection of the plurality of blocks. A segment comprises a connector between multiple blocks and other segments and segments are connected via the ports of blocks or other segments. Communications between blocks is packet based, each packet including at least a destination block. The packet includes at least one of data, packet/message identification and padding. Blocks have an associated address. A block has one or more input ports and one or more output ports. Segments include means for routing packets to destinations. Each block and segment includes properties. Properties include one or more of clocks, bandwidth, bit widths, and latencies. The plurality of segments for multiple packets to be active on different segments. A single segment includes a plurality of ports for multiple packets to be active on different ports of the segment.

Claims54

Dependent claims

A system comprising:

a plurality of hardware blocks, each said hardware block performing a function and having at least one port for sending or receiving packets;
and
a plurality of segments providing interconnection of the plurality of hardware blocks and operative to route packets between one or more of said hardware blocks and other ones of said segments;
and wherein
each packet includes data to be delivered and identifies at least one destination of said packet, said destination selected from said plurality of hardware blocks and said plurality of segments;
at least one of said plurality of segments includes a plurality of ports such that multiple packets may be active on different ports of the at least one segment simultaneously;
and
at least some of said plurality of hardware blocks and at least one of said plurality of segments are integrated on a single chip.

5 more elements

A system comprising:

a first integrated circuitry block including at least one port, said first integrated circuitry block associated with a first address;
a second integrated circuitry block including at least one port, said second integrated circuitry block associated with a second address;
and
a first segment in communication with said port of said first integrated circuitry block and said port of said second integrated circuitry block, said first segment facilitating intercommunication between said first integrated circuitry block and said second integrated circuitry block by routing packets between said first integrated circuitry block and said second integrated circuitry block based on said first address and said second address, each of said packets including a destination address and data to be delivered to said destination address;
and wherein
said first integrated circuitry block, said second integrated circuitry block, and said first segment are integrated on a chip;
a property of said first integrated circuitry block is different than the same said property of at least one of said second integrated circuitry block and said first segment;
and
said property is selected from the group comprising clock rate, bandwidth, bit width, and latency.

6 more elements

Dependencies are inferred from the claim text.

Method and apparatus for data movement in a system on a chip

Life of this patent

Method and apparatus for data movement in a system on a chip

Life of this patent

Abstract

Claims54