Memory systems and methods for translating memory addresses to temporal addresses in support of varying data widths

A memory module comprising:

• a memory die having N address lines and 2^N address locations, each address location having an internal data width and including W memory locations;
• means for dividing each of the 2^N address locations into W/2^B subsets of memory locations in the time domain, thereby dividing the memory die into 2^(N+B) memory subsets;
• means for providing an address signal specifying an N-bit physical address signal and a B-bit temporal address signal;
• means for selecting the address location specified by the physical address signal;
• means for masking access, based upon the temporal address signal, to at least one of the memory subsets of the address location specified by the physical address signal;
• and
• means for translating at least one first burst-order bit expressing a requested data-read order to at least one second burst-order bit expressing an internal data-read order.

A computer-readable medium having stored thereon a data structure defining a data-width translator adapted to translate data of a first width to data of a second width, the data structure comprising:

• first data representing an external memory interface defined to convey external data signals, of a first data width, and external address signals, the external address signals expressed as address bits;
• second data representing an internal memory interface defined to convey internal data signals of a second data width greater than the first data width;
• and
• third data representing a data-width translator coupled between the external and internal memory interfaces and defined to translate the external data signals to the internal data signals and the internal data signals to the external data signals, the third data further defined to translate at least one of the parallel address bits into a data-mask signal;
• wherein the data mask signal divides a physical address location into temporal subsets of the physical address location.