Digital phase relationship lock loop

A control unit for a first-in, first-out (FIFO) buffer for transferring data between a first clock domain corresponding to a first clock signal and a second clock domain corresponding to a second signal, the control unit comprising:

• a first clocked storage device clocked by the first clock signal, wherein the first clocked storage device is configured to store a first pointer to address the FIFO buffer;
• a second clocked storage device clocked by the second clock signal, wherein the second clocked storage device is configured to store a second pointer to address the FIFO buffer;
• a third clocked storage device clocked by the second clock signal, wherein the third clocked storage device is coupled to receive a third pointer that corresponds to the first pointer, the third pointer transmitted from the first clock domain to the second clock domain to be received by the third clocked storage device;
• a fourth clocked storage device having an input coupled to an output of the third clocked storage device and clocked by the second clock signal;
• a detect circuit that includes a sample storage device configured to store a sample history corresponding to a selected clock signal derived from one of the first clock signal or the second clock signal, wherein the sample history stored in the sample storage device includes samples from a plurality of clock cycles of the selected clock signal, and wherein the detect circuit is configured to predict a first phase relationship between the first clock signal and the second clock signal for a given clock cycle responsive to the sample history, and wherein the phase relationship between the first clock signal and the second clock signal is different each clock cycle during use;
• and
• a mode control unit configured to determine whether or not a transition in a value of the third pointer meets the setup and hold requirements of the third clocked storage device in the given clock cycle according to the first phase relationship between the second clock signal and the third clock signal as predicted by the detect circuit, and wherein the mode control unit is configured to select the output of the third clocked storage device to be compared to the second pointer responsive to determining that the transition in the value does meet the setup and hold requirements.