Method and device for three-dimensional path planning to avoid obstacles using multiple planes
AssigneeHoneywell International Inc.
InventorsKartik B. Ariyur, Eric Lautenschlager, Michael R. Elgersma
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AssigneeHoneywell International Inc.
InventorsKartik B. Ariyur, Eric Lautenschlager, Michael R. Elgersma
Estimating the term…
An obstacle-avoidance-processor chip for three-dimensional path planning comprises an analog processing circuit and at least two analog-resistive-grid networks. The analog processing circuit is communicatively coupled to receive data from an inertial measurement unit and from at least one obstacle-detection sensor. The analog processing circuit is configured to construct a three-dimensional obstacle map of an environment based on the received data. The at least two analog-resistive-grid networks are configured to map obstacles in at least two respective non-parallel planes in the constructed three-dimensional obstacle map. The at least two analog-resistive-grid networks form a quasi-three-dimensional representation of the environment. The obstacle-avoidance-processor chip generates information indicative of a three-dimensional unobstructed path in the environment based on the obstacle maps.
An obstacle-avoidance-processor chip for three-dimensional path planning, the obstacle-avoidance-processor chip comprising:
An integrated module for three-dimensional path planning, the integrated module comprising:
A method of planning an unobstructed three-dimensional path for a vehicle, the method comprising:
Dependencies are inferred from the claim text.