Image processing circuit and multi-function apparatus
AssigneeSeiko Epson Corporation
InventorToyoaki Kuwahara
Life of this patent
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Abstract
An image processing circuit for processing a two-dimensional image includes: a rearrangement unit rearranging pixels included in an input two-dimensional image; a main memory storing the rearranged two-dimensional image; and an image processor processing the two-dimensional image stored in the main memory. Here, the rearrangement unit rearranges the pixels so that when the two-dimensional image is divided into a plurality of blocks, the pixels included in the same block should be stored in an area specified by the same row address in the main memory.
Claims7
An image processing circuit for processing a two-dimensional image, comprising:
- a rearrangement unit rearranging pixels included in an input two-dimensional image;
- a main memory storing the rearranged two-dimensional image;
- and
- an image processor processing the two-dimensional image stored in the main memory,
- wherein the rearrangement unit rearranges the pixels so that when the two-dimensional image is divided into a plurality of blocks, the pixels included in the same block should be stored in an area specified by the same row address in the main memory.
A multi-function apparatus having a scanner and an image processing circuit for processing a two-dimensional scanned image read by the scanner, comprising:
- a rearrangement unit rearranging pixels included in the two-dimensional scanned image input from the scanner;
- a main memory storing the rearranged two-dimensional scanned image;
- and
- an image processor processing the two-dimensional image stored in the main memory,
- wherein the rearrangement unit rearranges the pixels so that when the two-dimensional scanned image is divided into a plurality of blocks, the pixels included in the same block should be stored in an area specified by the same row address in the main memory.
Dependencies are inferred from the claim text.