System and method of controlling power consumption in a digital phase locked loop (DPLL)

An apparatus, comprising:

• a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, and further adapted to maintain substantially the same temporal relationship of the triggering edges of the reference clock when switching between the distinct frequency clocks;
• and
• a phase locked loop (PLL) circuit adapted to establish a predetermined phase relationship between an input signal and an output signal using the reference clock, wherein the programmable frequency device comprises a circuit adapted to asynchronously receive an input frequency selection control signal that indicates a selection among the distinct frequency clocks for the reference clock, and synchronously generate an output frequency selection control signal that causes the selection of the reference clock at a particular time, and wherein the circuit generates the output frequency selection control signal once a period of one of said distinct frequency clocks.

An apparatus, comprising:

• a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, and further adapted to maintain substantially the same temporal relationship of the triggering edges of the reference clock when switching between the distinct frequency clocks;
• and
• a phase locked loop (PLL) circuit adapted to establish a predetermined phase relationship between an input signal and an output signal using the reference clock, wherein the programmable frequency device comprises a circuit adapted to asynchronously receive an input frequency selection control signal that indicates a selection among the distinct frequency clocks for the reference clock, and synchronously generate an output frequency selection control signal that causes the selection of the reference clock at a particular time, and wherein the phase locked loop (PLL) comprises a filter including a transfer function based on the output frequency selection control signal.

An apparatus, comprising:

• a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, and further adapted to maintain substantially the same temporal relationship of the triggering edges of the reference clock when switching between the distinct frequency clocks;
• and
• a phase locked loop (PLL) circuit adapted to establish a predetermined phase relationship between an input signal and an output signal using the reference clock, wherein the programmable frequency device comprises a circuit adapted to asynchronously receive an input frequency selection control signal that indicates a selection among the distinct frequency clocks for the reference clock, and synchronously generate an output frequency selection control signal that causes the selection of the reference clock at a particular time, wherein the phase locked loop (PLL) comprises an accumulator adapted to generate a first signal related to a coarse value of the phase of the output signal, and a time-to-digital converter (TDC) adapted to generate a second signal related to a fine value of the phase of the output signal, and a device adapted to generate a feedback phase signal related to a combination of the first and second signals, and wherein a delay in generating the feedback phase signal is based on the output frequency selection control signal.

An apparatus, comprising:

• means for receiving a raw reference clock and generating therefrom a set of distinct frequency clocks, wherein the raw reference clock has a plurality of edges, wherein each of the frequency clocks of the set has a plurality of edges, and wherein the means is also for selecting a first of the frequency clocks of the set and for outputting the selected frequency clock as the reference clock and then switching to select a second of the frequency clocks and for outputting the second selected frequency clock as the reference clock such that all edges of the reference clock are substantially time aligned with edges of the raw reference clock both before and after the switching;
• and
• a Digital Phase Locked Loop (DPLL) comprising an input accumulator and a Time-to-Digital Converter (TDC), wherein the input accumulator is adapted to receive a DPLL input signal and the reference clock, and wherein the TDC is adapted to receive a DPLL output signal and the reference clock.

A non-transitory processor-readable medium storing processor-readable instructions, wherein execution of the processor-readable instructions is for:

• (a) causing a frequency controller to send a programmable frequency device an input frequency selection control signal such that the programmable frequency device switches from outputting a first frequency clock as a reference clock to outputting a second frequency clock as the reference clock, wherein the programmable frequency device receives a raw reference clock and generates therefrom the first frequency clock and the second frequency clock, wherein the raw reference clock has a plurality of edges, wherein the reference clock as a plurality of edges, and wherein the switching occurs such that all edges of the reference clock are substantially time aligned with edges of the raw reference clock both before and after the switching.