OFDM demodulation device

An OFDM (Orthogonal Frequency Division Multiplexing) demodulator in a receiving apparatus for receiving an OFDM signal, wherein the OFDM signal is a signal in which a scattered pilot signal is placed at a prescribed symbol interval in a time axis direction and at a prescribed carrier interval in a frequency axis direction, a continuous pilot signal and a control information signal are placed at a prescribed carrier position, and an information transmission signal is placed in a remaining portion, the OFDM demodulator comprising:

• an FFT (Fast Fourier Transform) circuit for performing a fast Fourier transform on the OFDM signal;
• a circuit for extracting a scattered pilot signal from the fast Fourier transformed signal;
• a circuit for adding a phase to the extracted scattered pilot signal based on a position of the scattered pilot signal from a transmitting party;
• a memory for temporarily storing the phase-added scattered pilot signal and the information transmission signal;
• a memory interface for conducting write operation to the memory at a prescribed timing, starting read operation when a prescribed number of scattered pilot signals have been written and outputting the scattered pilot signals, and starting read operation at another timing and outputting the written information transmission signal;
• a carrier interpolation circuit for matching the phase of the scattered pilot signals received from the memory interface and performing interpolation in a time axis direction and a frequency axis direction;
• a complex division circuit for performing at a prescribed timing a complex division of the information transmission signal received from the memory interface by a result obtained from the carrier interpolation circuit;
• a plurality of circuits for performing interpolation in the time axis direction, and the plurality of circuits being selectable according to a reception condition, wherein one of the circuits for performing interpolation in the time axis direction uses a diagonal interpolation method;
• and
• a circuit for detecting an end in the diagonal interpolation method;
• a circuit for storing data at the end;
• a circuit for detecting a portion relating to data resulting from frequency axis interpolation at the end;
• and a circuit for replacing the portion relating to the data resulting from the frequency axis interpolation with the data at the end.

An OFDM (Orthogonal Frequency Division Multiplexing) demodulator in a receiving apparatus for receiving an OFDM signal, wherein the OFDM signal is a signal in which a scattered pilot signal is placed at a prescribed symbol interval in a time axis direction and at a prescribed carrier interval in a frequency axis direction, a continuous pilot signal and a control information signal are placed at a prescribed carrier position, and an information transmission signal is placed in a remaining portion, the OFDM demodulator comprising:

• an FFT Fast Fourier Transform circuit for performing a fast Fourier transform on the OFDM signal;
• a circuit for extracting a scattered pilot signal from the fast Fourier transformed signal;
• a circuit for adding a phase to the extracted scattered pilot signal based on a position of the scattered pilot signal from a transmitting party;
• a memory for temporarily storing the phase-added scattered pilot signal and the information transmission signal;
• a memos interface for conducting write operation to the memory at a prescribed min starting read operation when a prescribed number of scattered pilot signals have been written and outputting the scattered pilot signals, and starting read operation at another timing and outputting the written information transmission signal;
• a carrier interpolation circuit for matching the phase of the scattered pilot signals received from the memory interface and performing interpolation in a time axis direction and a frequency axis direction;
• a complex division circuit for performing at a prescribed timing a complex division of the information transmission signal received from the memory interface by a result obtained from the carrier interpolation circuit;
• a circuit for prestoring an initial address of a memory region in the memory;
• a first counter showing a current read symbol position and being incremented by one on a symbol by symbol basis;
• a second counter showing from which symbol a scattered pilot signal is to be retrieved with respect to a value of the first counter, and being incremented by one on a symbol by symbol basis in a range of 0 through 3;
• a third counter being initialized by a value of the second counter and incremented by one every time a scattered pilot signal is read;
• an offset retrieving circuit for selecting the initial address of the memory region by using a value of the first counter and a value of the third counter;
• and
• a fourth counter being always initialized at a beginning of a symbol and being incremented by one every time a scattered pilot signal is read, wherein
• a sum of an output of the offset retrieving circuit and a value of the fourth counter is used as a read address for reading a scattered pilot signal from the memory.

An OFDM (Orthogonal Frequency Division Multiplexing) demodulator in a receiving apparatus for receiving an OFDM signal, wherein the OFDM signal is a signal in which a scattered pilot signal is placed at a prescribed symbol interval in a time axis direction and at a prescribed carrier interval in a frequency axis direction, a continuous pilot signal and a control information signal are placed at a prescribed carrier position, and an information transmission signal is placed in a remaining portion, the OFDM demodulator comprising:

• an FFT (Fast Fourier Transform) circuit for performing a fast Fourier transform on the OFDM signal;
• a circuit for extracting a scattered pilot signal from the fast Fourier transformed signal;
• a circuit for adding a phase to the extracted scattered pilot signal based on a position of the scattered pilot signal from a transmitting party;
• a memory for temporarily storing the phase-added scattered pilot signal and the information transmission signal;
• a memory interface for conducting write operation to the memory at a prescribed timing, starting read operation when a prescribed number of scattered pilot signals have been written and outputting the scattered pilot signals, and starting read operation at another timing and outputting the written information transmission signal;
• a carrier interpolation circuit for matching the phase of the scattered pilot signals received from the memory interface and performing interpolation in a time axis direction and a frequency axis direction;
• a complex division circuit for performing at a prescribed timing a complex division of the information transmission signal received from the memory interface by a result obtained from the carrier interpolation circuit;
• a frequency filter for interpolating a scattered pilot signal in a frequency axis direction, wherein the frequency filter includes a circuit for storing a selection result of a time axis interpolation method, a first counter for counting input data while initializing input data every time a symbol ends, an end signal generation circuit for generating a 1-symbol end signal according to a value of the first counter, a second counter being incremented on a symbol by symbol basis by the end signal generation circuit, an end processing control circuit for conducting end control of a diagonal interpolation method, and a data output selection control circuit being controlled by using an output of the second counter, the stored selection result of the time axis interpolation method, and the end processing control circuit, for recognizing an interval between valid data signals which varies depending on a time axis interpolation method, and selecting valid data input and 0 insertion.

An OFDM (Orthogonal Frequency Division Multiplexing) demodulator in a receiving apparatus for receiving an OFDM signal, wherein the OFDM signal is a signal in which a scattered pilot signal is placed at a prescribed symbol interval in a time axis direction and at a prescribed carrier interval in a frequency axis direction, a continuous pilot signal and a control information signal are placed at a prescribed carrier position, and an information transmission signal is placed in a remaining portion, the OFDM demodulator comprising:

• an FFT (Fast Fourier Transform) circuit for performing a fast Fourier transform on the OFDM signal;
• a circuit for extracting a scattered pilot signal from the fast Fourier transformed signal;
• a circuit for adding a phase to the extracted scattered pilot signal based on a position of the scattered pilot signal from a transmitting party;
• a memory for temporarily storing the phase-added scattered pilot signal and the information transmission signal;
• a memory interface for conducting write operation to the memory at a prescribed timing, starting read operation when a prescribed number of scattered pilot signals have been written and outputting the scattered pilot signals, and starting read operation at another timing and outputting the written information transmission signal;
• a carrier interpolation circuit for matching the phase of the scattered pilot signals received from the memory interface and performing interpolation in a time axis direction and a frequency axis direction;
• and
• a complex division circuit for performing at a prescribed timing a complex division of the information transmission signal received from the memory interface by a result obtained from the carrier interpolation circuit,
• wherein
• the memory is divided into two memory regions for an information transmission signal and two memory regions for a scattered pilot signal,
• a clock is supplied to all the memory regions in one mode and a clock is supplied to either the memory regions for an information transmission signal or the memory regions for a scattered pilot signal in another mode,
• by providing a status for each memory region, the two memory regions for a scattered pilot signal are used to store an information transmission signal when a received OFDM signal is in a differential mode, and are used to store a scattered pilot signal when a received OFDM signal is in a synchronous mode.

An OFDM (Orthogonal Frequency Division Multiplexing) demodulator in a receiving apparatus for receiving an OFDM signal, wherein the OFDM signal is a signal in which a scattered pilot signal is placed at a prescribed symbol interval in a time axis direction and at a prescribed carrier interval in a frequency axis direction, a continuous pilot signal and a control information signal are placed at a prescribed carrier position, and an information transmission signal is placed in a remaining portion, the OFDM demodulator comprising:

• an FFT (Fast Fourier Transform) circuit for performing a fast Fourier transform on the OFDM signal;
• a circuit for extracting a scattered pilot signal from the fast Fourier transformed signal;
• a circuit for adding a phase to the extracted scattered pilot signal based on a position of the scattered pilot signal from a transmitting party;
• a memory for temporarily storing the phase-added scattered pilot signal and the information transmission signal;
• a memory interface for conducting write operation to the memory at a prescribed timing, starting read operation when a prescribed number of scattered pilot signals have been written and outputting the scattered pilot signals, and starting read operation at another timing and outputting the written information transmission signal;
• a carrier interpolation circuit for matching the phase of the scattered pilot signals received from the memory interface and performing interpolation in a time axis direction and a frequency axis direction;
• and
• a complex division circuit for performing at a prescribed timing a complex division of the information transmission signal received from the memory interface by a result obtained from the carrier interpolation circuit,
• wherein when there are N independent read requests using a same scattered pilot signal and having different processing timings, each of M memory regions in the memory has N write completion statuses and N read completion statuses, where M and N are an integer.