Performing dynamic request routing based on broadcast queue depths

A method, in a data processing system, comprising:

• receiving, in a first processor chip of the data processing system, a plurality of first heartbeat signals from a plurality of second processor chips coupled to the first processor chip via one or more communication ports, wherein the plurality of first heartbeat signals have first queue depth information associated with respective processor chips of the plurality of second processor chips;
• storing the first queue depth information in a queue depth information data structure storage of the first processor chip;
• and
• performing routing of data from the first processor chip to a destination processor chip in the data processing system based on the first queue depth information stored in the queue depth information data structure storage, wherein:
• each first heartbeat signal in the plurality of first heartbeat signals is a signal broadcast by a corresponding second processor chip to the first processor chip and other second processor chips at a regular interval that is synchronized with a master processor chip through a synchronization process, and
• the first queue depth information for a current second processor chip comprises queue depth information for communication ports of the current second processor chip and queue depth information for communication ports of each of the other second processor chips to which the current second processor chip is directly coupled, queue depth information for communication ports of other processor chips to which the current second processor chip is indirectly coupled and which are present in a same processor book or different processor books of a same supernode, and queue depth information of additional processor chips in other supernodes that are indirectly coupled to the current second processor chip via the other second processor chips in the same processor book and different processor books of the same supernode.

A computer program product comprising a computer useable storage device having a computer readable program stored thereon, wherein the computer readable program, when executed in a data processing system, causes the data processing system to:

• receive, in a first processor chip of the data processing system, a plurality of first heartbeat signals from a plurality of second processor chips coupled to the first processor chip via one or more communication ports, wherein the plurality of first heartbeat signals have first queue depth information associated with respective processor chips of the plurality of second processor chips;
• store the first queue depth information in a queue depth information data structure storage of the first processor chip;
• and
• perform routing of data from the first processor chip to a destination processor chip in the data processing system based on the first queue depth information stored in the queue depth information data structure storage, wherein:
• each first heartbeat signal in the plurality of heartbeat signals is a signal broadcast by a corresponding second processor chip to the first processor chip and other second processor chips at a regular interval that is synchronized with a master processor chip through a synchronization process, and
• the first queue depth information for a current second processor chip comprises queue depth information for communication ports of the current second processor chip and queue depth information for communication ports of each of the other second processor chips to which the current second processor chip is directly coupled, queue depth information for communication ports of other processor chips to which the current second processor chip is indirectly coupled and which are present in a same processor book or different processor books of a same supernode, and queue depth information of additional processor chips in other supernodes that are indirectly coupled to the current second processor chip via the other second processor chips in the same processor book and different processor books of the same supernode.

A system, comprising:

• a plurality of processor chips;
• and
• a plurality of communication links directly coupling each processor chip in the plurality of processor chips to at least one other processor chip in the plurality of processor chips via bus connections, wherein each processor chip in the plurality of processor chips comprises heartbeat signal generation logic for generating a heartbeat signal for broadcasting over one or more communication links, in the plurality of communication links, coupled to the processor chip, wherein the heartbeat signal generation logic transmits queue depth information, associated with the one or more communication links, in the heartbeat signal broadcast over the one or more communication links to the plurality of other processor chips, wherein:
• the heartbeat signal is a signal broadcast by the processor chip to the plurality of other processor chips at a regular interval that is synchronized with a master processor chip through a synchronization process, and
• the queue depth information comprises queue depth information for the communication ports of the current processor chip and queue depth information for communication ports of each of the other processor chips to which the current processor chip is directly coupled, queue depth information for communication ports of other processor chips to which the current processor chip is indirectly coupled and which are present in a same processor book or different processor books of a same supernode, and queue depth information of additional processor chips in other supernodes that are indirectly coupled to the current processor chip via the other processor chips in the same processor book and different processor books of the same supernode.