Memory device, memory controller and memory system

A memory controller which controls a memory device having:

• a plurality of banks which respectively have memory cores including memory cell arrays and are selected by bank addresses;
• and a control circuit which controls operation of the memory cores within the plurality of banks, wherein
• each of the plurality of banks stores two-dimensionally arrayed data on the basis of a memory mapping of whose a memory logical space has a plurality of page areas that are selected by the bank addresses and row addresses, in which the plurality of page areas are arranged in rows and columns, and in which adjacent page areas are associated with different bank addresses, and
• the memory controller has a sequencer which, in response to an access request from a host device, determines that the access request is for horizontal access in which the two-dimensionally arrayed data is accessed in a horizontal direction, supplies a normal operation command corresponding to the horizontal access and the bank addresses to the memory device, and causes the memory cores within horizontal access target banks selected by the bank addresses to execute normal operation,
• the sequencer, in response to the access request, supplying refresh bank information for specifying banks other than the horizontal access target banks, and a background refresh command to the memory device, and, during the normal operation, causing the memory cores within refresh target banks related to the refresh bank information to execute the refresh operation.