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US 8,077,535 B2Granted
Memory refresh apparatus and method
AssigneeGoogle Inc.
InventorsKeith R. Schakel, Suresh Natarajan Rajan, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
Life of this patent
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Abstract
A system and method are provided. The system and method simulate a DRAM memory circuit using an interface circuit connected to a plurality of other DRAM memory circuits. In response to the receipt of a refresh control signal, a first refresh control signal is sent to a first subset of the plurality of other DRAM memory circuits and a second refresh control signal is sent to a second subset of the plurality of other DRAM memory circuits.
Claims34
A method, comprising:
- simulating at least one first DRAM memory circuit having a first memory capacity and a first row refresh cycle time (tRFC) using an interface circuit connected to a plurality of second DRAM memory circuits each having a second memory capacity that is smaller than the first memory capacity and a second tRFC that is less than the first tRFC;
- receiving, at the interface circuit, a refresh control signal from a memory controller;
- and
- in response to receiving the refresh control signal from the memory controller, sending from the interface circuit a first refresh control signal to a first subset of the second DRAM memory circuits and a second refresh control signal to a second subset of the second DRAM memory circuits, wherein the first and the second refresh control signals are sent at different times with the different times being selected so that refresh cycles of the second DRAM memory circuits initiated by the first and second refresh control signals complete within a time span specified by the first tRFC associated with the at least one first DRAM memory circuit.
1 more element
An apparatus, comprising:
- a plurality of dynamic random access memory (DRAM) memory circuits each having a first memory capacity and a first row refresh cycle time (tRFC);
- and
- an interface circuit operable to:
- communicate with the plurality of DRAM memory circuits and a system;
- emulate at least one memory circuit having a second memory capacity and a second tRF'C, the first memory capacity being smaller than the second memory capacity and the first tRFC being less than the second tRFC;
- receive a refresh control signal from the system;
- and
- send, in response to receiving the refresh control signal from the system, a first refresh to a control signal to a first subset of the DRAM memory circuits and a second refresh control signal second subset of the DRAM memory circuits, wherein the interface circuit is operable to send the first and the second refresh control signals at different times with the different times being selected so that refresh cycles of the DRAM memory circuits initiated by the first and second refresh control signals complete within a time span specified by the second tRFC associated with the at least one emulated memory circuit.
5 more elements
An apparatus, comprising:
- a plurality of physical DRAM memory circuits;
- and
- an interface circuit in communication with the plurality of physical DRAM memory circuits, the interlace circuit operable to:
- communicate with a system;
- communicate with the plurality of physical DRAM memory circuits;
- emulate at least one memory circuit having a second memory capacity and a second tRFC, the first memory capacity being smaller than the second memory capacity and the first tRFC being less than the second tRFC;
- receive a refresh control signal from the system;
- and
- send, in response to receiving the refresh control signal from the system, a first refresh control signal to a first subset of the DRAM memory circuits and a second refresh control signal to a second subset of the DRAM memory circuits, wherein the interface circuit is operable to send the first and the second refresh control signals at different times with the different times being selected so that refresh cycles of the DRAM memory circuits initiated by the first and second refresh control signals complete within a time span specified by the second tRFC associated with the at least one emulated memory circuit.
6 more elements
Dependencies are inferred from the claim text.