Memory and method for sensing data in a memory using complementary sensing scheme

#Related subject matter is found in our copending patent application Ser. No. 11/218,135, filed Sep. 1, 2005, entitled “MEMORY WITH ROBUST DATA SENSING AND METHOD FOR SENSING DATA” and assigned to the assignee hereof.

#The invention relates generally to memories, and more particularly to sense amplifiers for memories.

#Integrated circuit memories are organized into one or more arrays each including a matrix of rows and columns, with a memory cell located at each intersection of a row and a column. When accessed during a read cycle, the memory decodes an address to enable one row line. The memory cells on the enabled row line provide their contents onto bit lines, or more commonly, onto differential bit line pairs. Column decoding is used to select a subset of the bit line pairs to connect to one or more differential data line pairs. A sense amplifier connected to each data line pair detects a logic state of the differential signal and amplifies it. The amplified signal may then be provided to an output terminal of the memory, or further decoding may take place.

#The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawing, in which like reference numbers indicate similar or identical items.

#FIG. 1 illustrates in partial block diagram, partial logic diagram, and partial schematic form a memory according to the present invention;

#FIG. 2 illustrates a timing diagram useful in understanding the operation of the memory of FIG. 1; and

#In one form a method is disclosed for sensing data in a memory. A local data line pair is precharged to a first logic state and a global data line pair is precharged to a second logic state. A selected memory cell is coupled to the local data line pair to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.

#According to one aspect of this method the differential global data line voltage is subsequently amplified to form an amplified differential global data line voltage. In this case a data output signal may be outputted in response to the amplified differential global data line voltage. The data output signal may further be outputted in response to a voltage on a predetermined global data line of the global data line pair. In another case the differential global data line voltage may be subsequently amplified while the differential local data line voltage continues to be amplified, and the global data line voltage may continue to be amplified while the differential local data line voltage ceases to be amplified. In yet another case a global sense amplifier may be subsequently activated after a programmable delay determined in response to a state of at least one fuse.

#According to another aspect of this method the local data line pair is precharged to a logic high state and the global data line pair is precharged to a logic low state.