Semiconductor memory device

A semiconductor memory device, wherein bit lines for reading memory data have a hierarchical bit line structure, the device comprising:

• a plurality of columns including a plurality of local blocks having a plurality of memory cells and a local read bit line, the plurality of memory cells being connected to the local read bit line and the local blocks in each of the plurality of columns being arranged in a direction along the local read bit line;
• a global read bit line provided, corresponding to at least one column;
• and
• a local amplifier for driving a global read bit line in accordance with a signal output from each local block,
• wherein each memory cell includes:
• a holding circuit for holding memory data;
• and
• a read output circuit for outputting a signal corresponding to the data held by the holding circuit to a single local read bit line,
• when the held data is read, only one memory cell in one local block is activated in each column, and
• the local amplifier includes:
• a logic element for outputting a signal corresponding to a potential of a local read bit line when the local amplifier is selected by a column select signal;
• and
• a drive transistor in which the presence or absence of application of a predetermined potential is controlled in accordance with an output signal of the logic element, and an output terminal thereof is connected to a global read bit line.