Low power SSTL memory controller

A system comprising:

• a circuit board;
• a plurality of Dynamic Random Access Memory (DRAM) devices coupled to the circuit board;
• and
• an integrated circuit device having configurable resources, the integrated circuit device coupled to the circuit board and electrically coupled to the DRAM devices so as to form a plurality of parallel channels of DRAM memory, the integrated circuit device configured as a memory controller that includes a plurality of bi-directional pins that are electrically coupled to the DRAM devices, the memory controller including an input buffer circuit that is operable to receive SSTL-compliant input and an output buffer that is operable to generate SSTL-compliant output, wherein the input buffer circuit comprises a first single-ended buffer coupled to a first voltage level and to a ground voltage, the first single-ended buffer having an input coupled to one of the bi-directional pins and having an output coupled to control logic of the memory controller,
• wherein the input buffer circuit further comprises at least one additional buffer comprising an input coupled to one of the bi-directional pins,
• wherein the at least one additional buffer selectively couples the input to the control logic according to whether a power connection of the at least one additional buffer is connected to a voltage level sufficient for the at least one additional buffer to be operable.

A method for controlling a memory device comprising:

• defining a configuration of a memory controller so as to select an input buffer circuit having a single-ended buffer and select an SSTL-compliant output buffer, where the single-ended buffer and the SSTL-compliant output buffer are powered at a first voltage Level;
• and
• configuring an integrated circuit device using the defined configuration so as to form a memory controller having the single-ended buffer and having the SSTL-compliant output buffer,
• wherein defining a configuration of a memory controller further comprises selecting an SSTL18 compliant output buffer, wherein the input buffer circuit is not fully compliant with the SSTL18 specification.