Semiconductor memory device with a stacked gate including a charge storage layer and a control gate and method of controlling the same

A semiconductor memory device comprising:

• a transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load;
• and
• a control circuit which includes a logic circuit to which a first signal and a second signal are input and, on the basis of an operation result of the logic circuit, causes the p-type MOS transistor to turn on and off,
• wherein the logic circuit, when receiving an instruction to transfer the second voltage to the load, outputs the operation result to turn the p-type MOS transistor on and then, during the transfer to the load, outputs the operation result to turn the p-type MOS transistor off, thereby making the gate of the n-type MOS transistor float at the first voltage.