Distributed VDC for SRAM memory

An integrated circuit structure comprising:

• a memory comprising:
• a first memory macro;
• a first power block connected to the first memory macro and configured to provide a regulated voltage to the first memory macro, the first power block comprising a first input and a first output;
• a second memory macro identical to the first memory macro;
• a second power block substantially identical to the first power block, wherein the second power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro, and wherein the second power block comprises a second input and a second output;
• and
• a control block comprising:
• a first compensation module configured to stabilize an output voltage for a first group of memory macros which include the first memory macro;
• and
• a second compensation module configured to stabilize an output voltage for a second group of memory macros which include the second memory macro.