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US 8,077,516 B2Granted
Method and apparatus for accessing memory with read error by changing comparison
AssigneeMacronix International Co., Ltd.
InventorsChun-Hsiung Hung, Han-Sung Chen
Life of this patent
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Abstract
In response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code generated in response to a read command, the comparison process is changed, between i) a value representing accessed data and ii) a reference applied to such accesses to distinguish between logical levels. For example, the ratio of resistances characterizing input circuits of a sense amplifier and/or the read bias arrangement and/or a read reference of a memory integrated circuit is/are changed.
Claims23
A method of reading a memory, comprising:
- in response to a read command, the memory performing:
- generating a first check code based on accessing a plurality of data bits stored on the memory;
- accessing a second check code stored on the memory as a plurality of check bits associated with the plurality of data bits;
- checking whether the first check code and the second check code are in agreement;
- and
- responsive to disagreement between the first check code and the second check code, changing a comparison between i) at least one value representing at least one of the plurality of data bits stored on the memory, said at least one value accessed by a read bias arrangement applied on the memory, and ii) at least one reference applied to accesses of the data bits stored on the memory, said at least one reference and the comparison distinguishing between logical levels represented by said at least one value, including:
- changing the comparison by changing a ratio of a first resistance and a second resistance, the first resistance characterizing a first input circuit of a sense amplifier that receives said at least one value, the second resistance characterizing a second input circuit of the sense amplifier that receives said at least one reference.
4 more elements
A memory, comprising:
- a memory array;
- and
- control circuitry coupled to the memory array, the control circuitry responsive to a read command by performing:
- generating a first check code based on accessing a plurality of data bits stored on the memory array;
- accessing a second check code stored on the memory as a plurality of check bits associated with the plurality of data bits;
- checking whether the first check code and the second check code are in agreement;
- responsive to disagreement between the first check code and the second check code, changing a comparison between i) at least one value representing at least one of the plurality of data bits stored on the memory array, said at least one value accessed by a read bias arrangement applied to the memory array, and ii) at least one reference applied to accesses of the data bits stored on the memory array, said at least one reference and the comparison distinguishing between logical levels represented by said at least one value, including:
- changing the comparison by changing a ratio of a first resistance and a second resistance, the first resistance characterizing a first input circuit of a sense amplifier that receives said at least one value, the second resistance characterizing a second input circuit of the sense amplifier that receives said at least one reference.
5 more elements
A memory integrated circuit, comprising:
- a memory array means;
- and
- control circuitry means coupled to the memory array means, the control circuitry means responsive to a read command, comprising:
- means for generating a first check code based on accessing a plurality of data bits stored on the memory integrated circuit;
- means for accessing a second check code stored on the memory integrated circuit as a plurality of check bits associated with the plurality of data bits;
- means for checking whether the first check code and the second check code are in agreement;
- and
- means, responsive to disagreement between the first check code and the second check code, for changing a comparison between i) at least one value representing at least one of the plurality of data bits stored on the memory integrated circuit, said at least one value accessed by a read bias arrangement applied on the memory integrated circuit, and ii) at least one reference applied to accesses of the data bits stored on the memory integrated circuit, said at least one reference and the comparison distinguishing between logical levels represented by said at least one value, including:
- means for changing a ratio of a first resistance and a second resistance, the first resistance characterizing a first input circuit of a sense amplifier that receives said at least one value, the second resistance characterizing a second input circuit of the sense amplifier that receives said at least one reference.
6 more elements
Dependencies are inferred from the claim text.