Dynamic multistate memory write driver
AssigneeGrandis, Inc.
InventorAdrian E. Ong
Life of this patent
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Abstract
A circuit includes, in part, a multitude of magnetic random access memory cells, one or more column decoders, one or more row decoders, and a write driver circuit. The write driver circuit is responsive to data signal as well as to read/write signals. During writing of a first data to a selected magnetic random access memory cell, the write driver circuit causes the first signal line to be at a second voltage and the second signal line to be at the first voltage. The second voltage is greater than the first voltage. During writing of a second data to the selected magnetic random access memory cell, the write driver circuit cause the first signal line to be at a third voltage and the second signal line to be at the second voltage. The third voltage is smaller than the first voltage.
Claims20
A circuit comprising:
- a plurality of magnetic random access memory cells each comprising a magnetic tunnel junction structure and an associated select transistor;
- one or more column decoders;
- one or more row decoders;
- a write driver circuit responsive to a data signal and read/write signals, the write driver circuit adapted to:
- cause a first signal line coupled to a first one of the magnetic random access memory cells to be tristated, and to cause a second signal line coupled to the first one of the magnetic random access memory cell to be at a first voltage during a read operation;
- cause the first signal line to be at a second voltage and the second signal line to be at the first voltage during a first write operation, wherein said second voltage is greater than said first voltage;
- and
- cause the first signal line to be at a third voltage and the second signal line to be at the second voltage during a second write operation, wherein said third voltage is smaller than said first voltage.
A method of controlling operation of a plurality of magnetic random access memory cells each comprising a magnetic tunnel junction structure and an associated select transistor, the method comprising:
- selecting a first one of the magnetic random access memory cells;
- causing a first signal line coupled to the selected magnetic random access memory cell to be tristated during a read operation;
- causing a second signal line coupled to the selected magnetic random access memory cell to be at a first voltage during the read operation;
- causing the first signal line to be at a second voltage during a first write operation;
- causing the second signal line to be at the first voltage during the first write operation, wherein said second voltage is greater than the first voltage;
- causing the first signal line to be at a third voltage during a second write operation;
- and
- causing the second signal line to be at the second voltage during the second write operation, wherein said third voltage is smaller than said first voltage.
Dependencies are inferred from the claim text.