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US 8,077,501 B2Granted
Differential read and write architecture
AssigneeGrandis, Inc.
InventorAdrian E. Ong
Life of this patent
Estimating the term…
Abstract
A memory cell includes a pair of magnetic tunnel junctions and a pair of associated transistors. The magnetic tunnel junctions of the pair are differentially disposed so that in response to the applied voltages, when one them stores a logic one, the other one stores a logic zero. Accordingly, the read operation margin is increased by a factor of two. The true and complementary bit lines of the differential memory cell are coupled to a sense amplifier. Consequently, the need for using reference bit lines is eliminated.
Claims20
A memory cell comprising:
- a first magnetic tunnel junction having a first terminal coupled to a first signal line;
- a first transistor having a first current carrying terminal coupled to a second signal line and a second current carrying terminal coupled to a second terminal of the first magnetic tunnel junction;
- a second magnetic tunnel junction having a first terminal coupled to a third signal line;
- and
- a second transistor having a first current carrying terminal coupled to a fourth signal line and a second current carrying terminal coupled to a second terminal of the second magnetic tunnel junction, wherein gate terminals of said first and second transistors are coupled to one another.
2 more elements
A method of forming a memory cell, the method comprising:
- connecting a first terminal of a first magnetic tunnel junction to a first signal line;
- connecting a first current carrying terminal of a first transistor to a second terminal of the first magnetic tunnel junction;
- connecting a second current carrying terminal of the first transistor to a second signal line;
- connecting a first terminal of a second magnetic tunnel junction to a third signal line;
- connecting a first current carrying terminal of a second transistor to a second terminal of the second magnetic tunnel junction;
- connecting a second current carrying terminal of the second transistor to a fourth signal line;
- and
- connecting gate terminals of the first and second transistors to one another.
5 more elements
A memory cell comprising:
- a first magnetic tunnel junction having a first terminal coupled to a first signal line;
- a first transistor having a first current carrying terminal coupled to a second signal line and a second current carrying terminal coupled to a second terminal of the first magnetic tunnel junction;
- a second magnetic tunnel junction having a first terminal coupled to the first signal line;
- and
- a second transistor having a first current carrying terminal coupled to a third signal line and a second current carrying terminal coupled to a second terminal of the second magnetic tunnel junction, wherein gate terminals of said first and second transistors are coupled to one another.
2 more elements
A method of forming a memory cell, the method comprising:
- connecting a first terminal of a first magnetic tunnel junction to a first signal line;
- connecting a first current carrying terminal of a first transistor to a second terminal of the first magnetic tunnel junction;
- connecting a second current carrying terminal of the first transistor to a second signal line;
- connecting a first terminal of a second magnetic tunnel junction to the first signal line;
- connecting a first current carrying terminal of a second transistor to a second terminal of the second magnetic tunnel junction;
- connecting a second current carrying terminal of the second transistor to a third signal line;
- and
- connecting gate terminals of the first and second transistors to one another.
5 more elements
A memory cell comprising:
- a first magnetic tunnel junction having a first terminal coupled to a first signal line;
- a first transistor having a first current carrying terminal coupled to a second signal line and a second current carrying terminal coupled to a second terminal of the first magnetic tunnel junction;
- a second magnetic tunnel junction having a first terminal coupled to a third signal line;
- and
- a second transistor having a first current carrying terminal coupled to the second signal line and a second current carrying terminal coupled to a second terminal of the second magnetic tunnel junction, wherein gate terminals of said first and second transistors are coupled to one another.
2 more elements
A method of forming a memory cell, the method comprising:
- connecting a first terminal of a first magnetic tunnel junction to a first signal line;
- connecting a first current carrying terminal of a first transistor to a second terminal of the first magnetic tunnel junction;
- connecting a second current carrying terminal of the first transistor to a second signal line;
- connecting a first terminal of a second magnetic tunnel junction to a third signal line;
- connecting a first current carrying terminal of a second transistor to the second signal line;
- connecting a second current carrying terminal of the second transistor to a second terminal of the magnetic tunnel junction;
- and
- connecting gate terminals of the first and second transistors to one another.
5 more elements
Dependencies are inferred from the claim text.