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US 8,077,494 B2Granted
Ferroelectric memory with sub bit-lines connected to each other and to fixed potentials
AssigneePatrenella Capital Ltd., LLC
InventorHideaki Miyamoto
Life of this patent
Estimating the term…
Abstract
A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting respective sub bit lines with each other, and connects the sub bit lines of the nonselected subarrays with each other through the first transistor and connects the same to fixed potentials arranged on both ends of a memory cell array at least in a read operation.
Claims25
An apparatus, comprising:
- a memory cell array including a plurality of subarrays;
- a word line arranged in the memory cell array;
- a main bit line arranged to intersect with the word line;
- sub bit lines respectively arranged in each of the subarrays and configured to be coupled to the main bit line;
- a first transistor arranged between sub bit lines of nonselected subarrays to couple the sub bit lines of the nonselected subarrays to each other, wherein the first transistor has a first source/drain terminal directly connected to a first sub bit line of a first of the nonselected subarrays and has a second source/drain terminal directly connected to a second sub bit line of a second of the nonselected subarrays;
- and
- a second transistor configured to couple the sub bit line of one of the nonselected subarrays to a first fixed potential.
4 more elements
An apparatus, comprising:
- a memory cell array including a plurality of subarrays of memory cells;
- a first transistor arranged between sub bit lines of nonselected subarrays to couple the sub bit lines of the nonselected subarrays to each other, wherein the first transistor has a first terminal directly connected to a first sub bit line of a first of the nonselected subarrays and has a second terminal directly connected to a second sub bit line of a second of the nonselected subarrays;
- read circuitry coupled to the memory cell array and configured to read data stored in a memory cell of a selected one of the subarrays;
- and
- write circuitry coupled to the memory cell array and configured to rewrite the read data into the selected subarray.
2 more elements
A method of operating a memory, the method comprising:
- storing data in a selected subarray of a memory cell array having a plurality of subarrays of memory cells;
- using a first transistor, arranged between sub bit lines of nonselected subarrays, to couple the sub bit lines of the nonselected subarrays to each other, wherein the first transistor has a first terminal directly connected to a first sub bit line of a first of the nonselected subarrays and has a second terminal directly connected to a second sub bit line of a second of the nonselected subarrays;
- reading the stored data from a memory cell of the selected subarray;
- and
- rewriting the read data into the selected subarray.
2 more elements
An apparatus, comprising:
- means for storing data in a selected subarray of a memory cell array having a plurality of subarrays;
- a first transistor, arranged between sub bit lines of nonselected subarrays, to couple the sub bit lines of the nonselected subarrays to each other, wherein the first transistor has a first terminal directly connected to a first sub bit line of a first of the nonselected subarrays and has a second terminal directly connected to a second sub bit line of a second of the nonselected subarrays;
- means for reading the stored data from a memory cell of the selected subarray;
- and
- means for rewriting the read data into the selected subarray.
2 more elements
Dependencies are inferred from the claim text.