Method and system for mitigating risk of electrostatic discharge for a system on chip (SOC)

A method for controlling electrostatic discharge, the method comprising:

• in an integrated circuit comprising a plurality of portions electrically isolated from one another within said integrated circuit:
• routing ESD current via one or more of a plurality of paths within and/or on a package to which said integrated circuit is bonded, wherein said integrated circuit comprises one or more switching elements that are configurable during operation of said integrated circuit to select, during operation of said integrated circuit, one or more of said plurality of paths, and wherein said selected one or more of said plurality of paths:
• electrically couple two or more of said plurality of portions;
• and
• are characterized by low impedance at DC and high impedance at one or more frequencies utilized by circuits within said integrated circuit.