Scan driver for selectively performing progressive scanning and interlaced scanning and a display using the same
AssigneeSamsung Mobile Display Co., Ltd.
InventorDong-Yong Shin
Life of this patent
Estimating the term…
Abstract
A scan driver that selectively performs progressive scanning and interlaced scanning and a display using the same. The scan driver includes a shift register having a plurality of flip-flops arranged in series, an odd line selection unit having a plurality of NAND gates, and an even line selection unit having a plurality of NAND gates. In response to an odd line control signal and an even line control signal input to the odd line selection unit and the even line selection unit, respectively, the scan driver performs progressive scanning or interlaced scanning. The scan driver may also include a mode selection unit to selectively perform progressive scanning or interlaced scanning in response to a mode selection signal.
Claims17
A scan driver that selectively performs progressive scanning and interlaced scanning, comprising:
- a shift register for receiving a start pulse and a clock signal and outputting data at intervals of half of a cycle of the clock signal;
- a mode selection unit for receiving an output signal of a flip-flop of the shift register and performing a logical operation on the output signal of the flip-flop in response to a mode selection signal;
- an odd line selection unit for selecting an output signal of an odd-numbered flip-flop or an output signal of the mode selection unit in response to an odd line control signal;
- and
- an even line selection unit for selecting an output signal of an even-numbered flip-flop or the output signal of the mode selection unit in response to an even line control signal.
A scan driver that selectively performs progressive scanning and interlaced scanning, comprising:
- a shift register including a plurality of flip-flops connected in series, wherein odd-numbered flip-flops sample an input signal and output the sampled signal on a rising edge of a clock signal, and even-numbered flip-flops sample an input signal and output the sampled signal on a falling edge of the clock signal;
- a mode selection unit for performing a logical OR operation on output signals of adjacent flip-flops or masking the output signals of the flip-flops in response to a mode selection signal;
- an odd line selection unit for selecting an output signal of an odd-numbered flip-flop or an output signal of the mode selection unit in response to an odd line control signal;
- and
- an even line selection unit for selecting an output signal of an even-numbered flip-flop or the output signal of the mode selection unit in response to an even line control signal.
Dependencies are inferred from the claim text.