Method for driving an LCD device

A method for driving an LCD device, the LCD device comprising a plurality of rows of pixels, a plurality of sets of gate lines, and a plurality of data lines, the method comprising:

• sequentially enabling a plurality of gate signals corresponding to a plurality of odd gate lines in a first set of gate lines based on an ascending order during a first interval of a first set of intervals corresponding to an Nth frame;
• sequentially writing a plurality of data signals with a first polarity into a plurality of corresponding rows of pixels via the data lines based on the sequentially enabled gate signals corresponding to the odd gate lines in the first set of gate lines during the first interval of the first set of intervals corresponding to the Nth frame;
• setting a first common voltage to a storage capacitor common voltage during the first interval of the first set of intervals corresponding to the Nth frame;
• sequentially enabling a plurality of gate signals corresponding to a plurality of even gate lines in the first set of gate lines based on an ascending order during a second interval following the first interval of the first set of intervals corresponding to the Nth frame;
• sequentially writing a plurality of data signals with a second polarity into a plurality of corresponding rows of pixels via the data lines based on the sequentially enabled gate signals corresponding to the odd gate lines in the first set of gate lines during the second interval of the first set of intervals corresponding to the Nth frame;
• setting a second common voltage to a storage capacitor common voltage during the second interval of the first set of intervals corresponding to the Nth frame;
• sequentially enabling a plurality of gate signals corresponding to a plurality of even gate lines in a second set of gate lines based on a descending order during a first interval of a second set of intervals following the first set of intervals corresponding to the Nth frame;
• sequentially writing a plurality of data signals with a second polarity into a plurality of corresponding rows of pixels via the data lines based on the sequentially enabled gate signals corresponding to the even gate lines in the second set of gate lines during the first interval of the second set of intervals corresponding to the Nth frame;
• setting a second common voltage to a storage capacitor common voltage during the first interval of the second set of intervals corresponding to the Nth frame;
• sequentially enabling a plurality of gate signals corresponding to a plurality of odd gate lines in the second set of gate lines based on a descending order during a second interval following the first interval of the second set of intervals corresponding to the Nth frame;
• sequentially writing a plurality of data signals with the first polarity into a plurality of corresponding rows of pixels via the data lines based on the sequentially enabled gate signals corresponding to the odd gate lines in the second set of gate lines during the second interval of the second set of intervals corresponding to the Nth frame;
• and
• setting a first common voltage to a storage capacitor common voltage during the second interval of the second set of intervals corresponding to the Nth frame;
• wherein the first common voltage is different from the second common voltage, and the first polarity is opposite to the second polarity.