Two-step subranging ADC architecture

An apparatus comprising:

• a coarse reference ladder comprising:
• a first coarse reference ladder including a plurality of first unit resistors and a plurality of first taps to provide a first plurality of coarse references;
• and
• a second coarse reference ladder including a plurality of second unit resistors and a plurality of second taps to provide a second plurality of coarse references, wherein the plurality of first unit resistors are of a higher impedance than the plurality of second unit resistors;
• a coarse analog-to-digital converter (ADC) configured to receive an input voltage of a sample of an analog input signal and the first plurality of coarse references, the coarse ADC configured to perform a first comparison of the input voltage and the first plurality of coarse references and output a coarse output based on the first comparison;
• a switch matrix including a plurality of switches, the switch matrix configured to close a switch for a second tap based on the coarse output, the switch corresponding to a coarse reference of the second plurality of coarse references;
• a fine reference ladder configured to receive the coarse reference and output a plurality of fine references from a plurality of third taps of the fine reference ladder, the plurality of fine references determined based on the coarse reference;
• a fine ADC configured to receive the input voltage and the plurality of fine references from the plurality of third taps, wherein the fine ADC is configured perform a second comparison of the input voltage and the plurality of fine references and output a fine output based on the second comparison;
• and
• logic configured to output a digital output for the sample of the analog input sample based on the coarse output and the fine output.

An apparatus comprising:

• a coarse reference ladder comprising:
• a first coarse reference ladder including a plurality of first taps to provide a first plurality of coarse references;
• and
• a second coarse reference ladder including a plurality of second taps to provide a second plurality of coarse references;
• a coarse analog-to-digital converter (ADC) configured to receive an input voltage of a sample of an analog input signal and the first plurality of coarse references, the coarse ADC configured to perform a first comparison of the input voltage and the first plurality of coarse references and output a coarse output based on the first comparison;
• a switch matrix including a plurality of switches, the switch matrix configured to close a switch for a second tap based on the coarse output, the switch corresponding to a coarse reference of the second plurality of coarse references;
• a fine reference ladder configured to receive the coarse reference and output a plurality of fine references from a plurality of third taps of the fine reference ladder, the plurality of fine references determined based on the coarse reference, wherein the fine reference ladder comprises:
• a first fine reference ladder;
• a second fine reference ladder;
• and
• a buffer configured to buffer the second fine reference ladder from disturbances in the first fine reference ladder, wherein the second fine reference ladder is configured to provide a plurality of fine references determined based on the coarse reference;
• a fine ADC configured to receive the input voltage and the plurality of fine references from the plurality of third taps, wherein the fine ADC is configured perform a second comparison of the input voltage and the plurality of fine references and output a fine output based on the second comparison;
• and
• logic configured to output a digital output for the sample of the analog input sample based on the coarse output and the fine output.

A method comprising:

• providing a first plurality of coarse references via a plurality of first taps of a first coarse reference ladder including a plurality of first unit resistors;
• providing a second plurality of coarse references via a plurality of second taps of a second coarse reference ladder including a plurality of second unit resistors, wherein the plurality of first unit resistors are of a higher impedance than the plurality of second unit resistors;
• receiving an input voltage of a sample of an analog input signal and the first plurality of coarse references;
• performing a first comparison of the input voltage and the first plurality of coarse references and output a coarse output based on the first comparison;
• closing a switch in a switch matrix for a second tap based on the coarse output, the switch corresponding to a coarse reference of the second plurality of coarse references;
• receiving the coarse reference at a fine reference ladder;
• outputting a plurality of fine references from a plurality of third taps of the fine reference ladder, the plurality of fine references determined based on the coarse reference;
• receiving the input voltage and the plurality of fine references from the plurality of third taps;
• performing a second comparison of the input voltage and the plurality of fine references and output a fine output based on the second comparison;
• and
• outputting a digital output for the sample of the analog input sample based on the coarse output and the fine output.