Lock detection circuit for phase locked loop

A lock detector circuit for detecting a lock condition between a reference signal and a feedback signal, comprising:

• a first counter outputting a first counter value indicative of a number of clock cycles of the reference signal;
• a second counter outputting a second counter value indicative of a number of clock cycles of the feedback signal;
• an asynchronous comparator that receives the first and second counter values and generates a comparator output signal having a pulse width that is proportional to the difference between the first and second counter values;
• a pulse width detector that receives the comparator output signal and produces an output signal that is indicative of the relationship between the pulse width of the comparator output signal and a predetermined threshold value;
• and
• a state machine that receives the pulse width detector output signal and:
• when the pulse width detector output signal is indicative of the comparator output signal exceeding the predetermined threshold value, asynchronously resetting the first and second counters and providing a lock indication signal indicative of an out of lock condition, and
• when the pulse width detector output signal is indicative of the comparator output signal not exceeding the predetermined threshold value, and after detecting a predetermined number of consecutive increments of the first and second counters, providing a lock indication signal indicative of a lock condition.

A method of detecting a lock condition between a reference signal and a feedback signal, comprising:

• providing a first counter that outputs a first counter value indicative of a number of clock cycles of the reference signal;
• providing a second counter that outputs a second counter value indicative of a number of clock cycles of the feedback signal;
• comparing the first counter value and the second counter value and producing a first signal having a pulse width that is proportional to the difference between the first and second counter values;
• detecting the pulse width of the first signal and producing a second signal that is indicative of the relationship between the pulse width of the first signal and a predetermined threshold value;
• controlling the state of at least one lock indication signal according to the second signal;
• when the second signal is indicative of the first signal exceeding the predetermined threshold value, asynchronously resetting the first and second counters and providing a lock indication signal indicative of an out of lock condition;
• and
• when the second signal is indicative of the first signal not exceeding the predetermined threshold value, and after detecting a predetermined number of consecutive increments of the first and second counters, providing a lock indication signal indicative of a lock condition.