Fully differential amplifier with continuous-time offset reduction

A fully differential amplifier circuit, comprising:

• a first section for generating first and second output signals on first and second outputs from first and second input signals;
• a first negative feedback loop coupling the first output to a filter section, the first negative feedback loop adjusting the first output signal towards a common mode voltage level, and reducing an offset voltage of the first output signal;
• a second negative feedback loop coupling the second output to the filter section, the second negative feedback loop controlling the second negative feedback loop for adjusting the second output signal towards the common mode voltage level, and reducing an offset voltage of the second output signal,
• wherein the filter section acts as a low pass filter.

A fully differential amplifier circuit, comprising:

• a first differential cell for generating first and second output signals on first and second outputs from first and second input signals;
• a first negative feedback loop coupled to the first output of the first differential cell, the first negative feedback loop including a second differential cell for generating a first feedback signal, the feedback signal being for adjusting the first output signal towards a common mode voltage level, and for reducing an offset voltage of the first output signal;
• a second negative feedback loop coupled to the second output of the first differential cell, the second negative feedback loop including a third differential cell controlling the second negative feedback loop for generating a first feedback signal, the feedback signal being for adjusting the second output signal towards the common mode voltage level, and for reducing an offset voltage of the second output signal;
• and
• a low pass filter section positioned between the first differential cell and the second and third differential cells, the low pass filter section being for filtering the first and second feedback signals.

A method for setting a voltage level and cancelling an offset voltage of an amplified signal, comprising:

• generating first and second output signals from first and second input signals in a first section of a circuit;
• comparing the first and second output signals to a common mode voltage level for generating first and second feedback signals in second and third sections of the circuit;
• and
• filtering out from the feedback signals at least at least a portion thereof having a frequency lower than a data portion of the input signals using a filter section positioned between the first section and at least the second section, the feedback signals simultaneously adjusting the first and second output signals towards the common mode voltage level and reducing an offset voltage of the first and second output signals.