Sampling circuit
AssigneeHynix Semiconductor Inc.
InventorsJi-Wang Lee, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi, Jae-Min Jang, Chang-Kun Park
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Abstract
A sampling circuit for use in a semiconductor device, includes a first sampling unit configured to sample a data signal in synchronism with a reference clock signal and output a first output signal, a second sampling unit configured to sample a delayed data signal in synchronism with the reference clock signal and output a second output signal, and an output unit configured to combine the first and second output signals and output a sampling data signal.
Claims16
A sampling circuit, comprising:
- a first sampling unit configured to sample a data signal in synchronism with a reference clock signal and output a first output signal;
- a second sampling unit configured to sample a delayed data signal in synchronism with the reference clock signal and output a second output signal;
- and
- an output unit configured to combine the first and second output signals and output a sampling data signal,
- wherein the output unit includes:
- a combination unit configured to short output nodes of the first and second sampling units with a combination node;
- and
- a latch unit configured to latch a signal loaded at the combination node and output the sampling data signal.
A sampling circuit for use in a semiconductor device, comprising:
- a latch unit configured to latch a data signal in synchronism with a first edge of a reference clock signal and output a latched signal;
- a delay unit configured to delay the latched signal for a predetermined time and output a delayed signal;
- a first sampling unit configured to sample the latched signal in synchronism with a second edge of the reference clock signal and output a first sampling signal;
- a second sampling unit configured to sample the delayed signal in synchronism with the second edge of the reference clock signal and output a second sampling signal;
- and
- an output unit configured to combine the first and second sampling signals and output a sampling data signal.
A sampling circuit for use in a semiconductor device, comprising:
- a first sampling unit configured to sample a first data signal in synchronism with a reference clock signal and output a first sampling signal;
- a second sampling unit configured to sample a second data signal in synchronism with the reference clock signal and output a second sampling signal;
- a third sampling unit configured to sample a third data signal in synchronism with the reference clock signal and output a third sampling signal;
- a fourth sampling unit configured to sample a fourth data signal in synchronism with the reference clock signal and output a fourth sampling signal;
- and
- an output unit configured to combine the first to fourth sampling signals and output a sampling data signal,
- wherein the third and fourth data signals are generated by inverting and delaying the first and second data signals, respectively.
Dependencies are inferred from the claim text.