US 8,076,963 B2 · Delay-locked loop having a delay independent of input signal duty cycle variation

Abstract

A Delay-Locked Loop (DLL) uses a delay line to delay a first signal by a “delay time”, thereby generating a second signal. A capacitor is charged at a first rate starting at a first edge of first signal and continuing until an edge of the second signal. The capacitor is then discharged at a second rate until another edge of the first signal. A control loop controls the delay time such that the amount the capacitor is charged is the same as the amount the capacitor is discharged. The delay time is constant and is substantially independent of variations in the duty cycle of the first signal. In one example, duty cycle distortion cancellation is accomplished by changing the first rate proportionally with respect to changes in first signal duty cycle. In another example, the first and second rates are independent of the duty cycle of the first signal.

Claims22

Dependent claims

A method comprising:

(a) supplying a first signal to a delay line thereby producing a second signal, wherein the first signal has a duty cycle, wherein the second signal is a delayed version of the first signal, and wherein the second signal is delayed a delay time with respect to the first signal;
(b) starting to charge a capacitor upon a first edge of the first signal and continuing to charge the capacitor at a first rate until a first edge of the second signal;
(c) starting to discharge the capacitor upon the first edge of the second signal and continuing to discharge the capacitor at a second rate until a second edge of the first signal;
and
(d) controlling the delay time such that an amount the capacitor is charged in (b) is equal to an amount the capacitor is discharged in (c) and such that the delay time is substantially independent of changes in the duty cycle of the first signal.

2 more elements

A circuit comprising:

a capacitor that starts to charge upon a first edge of a first signal and continues to charge until a first edge of a second signal, and that starts to discharge upon the first edge of the second signal and continues to discharge until a second edge of the first signal;
a charging circuit that supplies charge to the capacitor;
a discharging circuit that removes charge from the capacitor;
a Voltage-Controlled Delay Line (VCDL) that has a first input lead, a second input lead, and an output lead, wherein the first signal is present on the first input lead of the VCDL, wherein the second input lead of the VCDL is coupled to the capacitor, wherein the second signal is present on the output lead of the VCDL, wherein the second signal is a delayed version of the first signal and is delayed a delay time with respect to the first signal, and wherein the delay time is substantially constant and independent of changes in the duty cycle of the first signal;
and
logic circuitry having a first input lead, a second input lead, and an output lead, wherein the first signal is present on the first input lead of the logic circuitry, wherein the second signal is present on the second input lead of the logic circuitry, and wherein the output lead of the logic circuitry is coupled to an input lead of the charging circuit.

3 more elements

Dependencies are inferred from the claim text.

Delay-locked loop having a delay independent of input signal duty cycle variation

Life of this patent

Delay-locked loop having a delay independent of input signal duty cycle variation

Life of this patent

Abstract

Claims22