Digital phase-locked loop with two-point modulation using an accumulator and a phase-to-digital converter

An apparatus comprising:

• a digital phase-locked loop (DPLL) comprising
• an accumulator operative to accumulate an input modulating signal to convert frequency to phase to obtain a first modulating signal;
• a scaling unit operative to scale the input modulating signal with a variable gain to obtain a second modulating signal, the scaling unit comprising:
• a gain computation unit operative to determine the variable gain based on the input modulating signal and a phase error signal provided to the loop filter;
• and
• a multiplier operative to multiply the input modulating signal with the variable gain;
• a phase-to-digital converter operative to determine a phase difference between a feedback signal and a reference signal and provide a phase difference signal;
• a first summer operative to sum the phase difference signal and the first modulating signal and provide a phase error signal;
• a loop filter operative to filter the phase error signal and provide a filtered phase error signal;
• and
• a second summer operative to sum the filtered phase error signal and the second modulating signal and provide a control signal for an oscillator.

A method of operating a digital phase-locked loop (DPLL) comprising:

• accumulating an input modulating signal to convert frequency to phase and obtain a first modulating signal;
• determining a variable gain based on the input modulating signal and a phase error signal provided to a loop filter;
• multiplying the input modulating signal with the variable gain to scale the input modulating signal and obtain a second modulating signal;
• determining a phase difference between a feedback signal and a reference signal to obtain a phase difference signal;
• summing the phase difference signal and the first modulating signal to obtain a phase error signal;
• filtering the phase error signal to obtain a filtered phase error signal;
• and
• summing the filtered phase error signal and the second modulating signal to obtain a control signal for an oscillator.

An apparatus comprising:

• means for accumulating an input modulating signal to convert frequency to phase and obtain a first modulating signal;
• means for determining a variable gain based on the input modulating signal and a phase error signal provided to a loop filter;
• means for multiplying the input modulating signal with the variable gain to scale the input modulating signal and obtain a second modulating signal;
• means for scaling the input modulating signal with a variable gain to obtain a second modulating signal;
• means for determining a phase difference between a feedback signal and a reference signal to obtain a phase difference signal;
• means for summing the phase difference signal and the first modulating signal to obtain a phase error signal;
• means for filtering the phase error signal to obtain a filtered phase error signal;
• and
• means for summing the filtered phase error signal and the second modulating signal to obtain a control signal for an oscillator.

A non-transitory processor-readable storage medium having stored thereon processor executable instructions configured to cause a processor to perform steps, comprising:

• accumulating an input modulating signal to convert frequency to phase and obtain a first modulating signal;
• determining a variable gain based on the input modulating signal and a phase error signal provided to a loop filter;
• multiplying the input modulating signal with the variable gain to scale the input modulating signal and obtain a second modulating signal;
• determining a phase difference between a feedback signal and a reference signal to obtain a phase difference signal;
• summing the phase difference signal and the first modulating signal to obtain a phase error signal;
• filtering the phase error signal to obtain a filtered phase error signal;
• and
• summing the filtered phase error signal and the second modulating signal to obtain a control signal for an oscillator.