Configurable logic device
AssigneeST-Ericsson SA
InventorsAlexander A. Danilin, Martinus T. Bennebroek, Sergei V. Sawitzki
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Abstract
The configurable logic device comprises a plurality of configurable logic cells (2). A configurable logic cell comprises a plurality of multi-bit registers (20a, 20b, 20c, 20d). At least one is accessible both in a parallel and in a serial fashion. A functional unit (30) therein is coupled to two or more of the registers and comprises a chain of functional unit segments (31, 31′) that each comprise an AND gate (33) and a 1-bit full adder (32) receiving an output of the AND-gate. An output selection facility (50) provides an output signal of the configurable logic cell selected from two or more input signals. At least one of the input signals is provided by one of the multi-bit registers, and another by the functional unit.
Claims14
A method comprising:
- providing a configurable logic device comprising a plurality of configurable logic cells, each configurable logic cell comprising a plurality of multi-bit registers, at least one multi-bit register being accessible both in a parallel and in a serial fashion;
- selectively coupling, using an input selection facility, an output of a first multi-bit register to the input of a second multi-bit register, the input selection facility causing a bit-shift-operation of the output of the second multi-bit register for each clock cycle;
- performing a temporal multiplication algorithm for multiplicands present on the inputs of the first multi-bit register;
- selectively coupling, using the input selection facility, the output of the first multi-bit register to the input of the first multi-bit register of another one of the configurable logic cells;
- and
- performing a spatial multiplication algorithm for multiplicands present on the inputs of the first multi-bit registers of the each configurable logic cell and the another one of the configurable logic cells.
A configurable logic device comprising:
- a plurality of configurable logic cells, each configurable logic cell comprising:
- a plurality of multi-bit registers, at least one being accessible both in a parallel and in a serial fashion;
- a functional unit coupled to two or more of the registers, comprising a chain of functional unit segments that each comprise an AND gate and a 1-bit full adder receiving an output of the AND gate;
- an output selection facility for providing an output signal of the configurable logic cell selected from two or more input signals, at least one of the input signals being provided by one of the multi-bit registers, and another provided by the functional unit, the output selection facility operable to receive an input signal from an input selection facility;
- and
- a routing structure selectively coupling the each configurable logic cell to one or more of its adjacent configurable routing cells.
Dependencies are inferred from the claim text.