Memory control circuit, memory control method, and integrated circuit
AssigneeCanon Kabushiki Kaisha
InventorsKohei Murayama, Takeshi Suzuki
Life of this patent
Estimating the term…
Abstract
Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for a memory to be accessed, at least one memory for which driving of the terminating resistor is to be suppressed, in accordance with the memory to be accessed.
Claims12
A memory control apparatus for controlling a plurality of memories, each of which includes a respective terminating circuit for preventing signal reflection in the corresponding memory, the memory control apparatus comprising:
- a memory command controller constructed to assert an On-Die Termination (ODT) enable signal, an ODT direction signal and an ODT device signal;
- a memory data controller constructed to exchange data with one of the plurality of memories based on a timing signal output by the memory command controller;
- and
- an ODT controller constructed to assert an ODT signal to each of the plurality of memories via a flip flop,
- wherein the memory command controller asserts the ODT enable signal in advance in order to adjust a delay of the flip flop.
A memory control method for controlling a plurality of memories, each of which includes a respective terminating circuit for preventing signal reflection in the corresponding memory, the method comprising:
- asserting an On-Die Termination (ODT) enable signal, an ODT direction signal and an ODT device signal;
- exchanging data with one of the plurality of memories based on a timing signal;
- and
- asserting an ODT signal to each of the plurality of memories via a flip flop,
- wherein the ODT enable signal is asserted in advance for adjusting a delay of the flip flop.
Dependencies are inferred from the claim text.