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US 8,076,911 B2Granted
Flash memory and related voltage regulator
AssigneeSamsung Electronics Co., Ltd.
InventorTakuya Ariki
Life of this patent
Estimating the term…
Abstract
A voltage regulator includes a voltage regulator unit configured to output a step voltage and a damping resistance switching unit coupled between a load and an output node of the voltage regulator and configured to select an optimal damping resistance value based on a required load capacity.
Claims14
A voltage regulator comprising:
- a voltage regulator unit configured to output a stepped driving voltage at an output node;
- and
- a damping resistance switching unit connected along a driving voltage path between a load and the output node of the voltage regulator unit, and configured to select a variable damping resistance value for the driving voltage path based on a required capacity for the load.
A voltage regulator comprising:
- a voltage regulator unit configured to output a stepped voltage at an output node;
- and
- a damping resistance switching unit connected between a load and the output node of the voltage regulator unit, and configured to select a variable damping resistance value based on a required capacity for the load,
- wherein the damping resistance switching unit comprises:
- first, second and third damping resistances connected in series between the output node of the voltage regulator unit and the load, wherein the first damping resistance has a resistance value twice as great as either the second damping resistance or the third damping resistance;
- a first CMOS transistor switch connected in parallel across the first damping resistance and comprising an NMOS transistor controlled by a first control signal and a PMOS transistor controlled by a first complementary control signal;
- a second CMOS transistor switch connected in parallel across a series combination of the first and second damping resistances and comprising an NMOS transistor controlled by a second control signal and a PMOS transistor controlled by a second complementary control signal;
- and
- a third CMOS transistor switch connected in parallel across a series combination of the first, second, and third damping resistances and comprising an NMOS transistor controlled by a third control signal and a PMOS transistor controlled by a third complementary control signal.
6 more elements
A flash memory device configured to operate in a first mode and a second mode and comprising a voltage regulator, wherein the voltage regulator comprises:
- a voltage regulator unit configured to output via a driving voltage path a stepped driving voltage to a load having a first capacity during the first mode and a second capacity during the second mode greater than the first capacity;
- and
- a damping resistance switching unit connected along the driving voltage path, and configured to apply a fixed damping resistance value to the driving voltage path during the first mode, and bypass the fixed damping resistance during the second mode.
Dependencies are inferred from the claim text.