Stacked semiconductor chips
AssigneeInfineon Technologies AG
InventorsMarkus Brunnbauer, Recai Sezi, Thorsten Meyer, Gottfried Beer
Life of this patent
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Abstract
Stacked semiconductor chips are disclosed. One embodiment provides a method including a first substrate having a first surface and an opposing second surface. The first substrate includes an array of first connection elements on the first surface of the first substrate. A second substrate has a first surface and an opposing second surface. The second substrate includes an array of second connection elements on the first surface of the second substrate. The first connection elements is attached to the second connection elements; and is thinning at least one of the first substrate and the second substrate after the attachment of the first connection elements to the second connection elements.
Claims18
A device, comprising:
- a first semiconductor chip having an array of first connection elements on a first surface of the first semiconductor chip;
- and
- a second semiconductor chip having an array of second connection elements on a first surface of the second semiconductor chip, wherein the first connection elements are attached to the second connection elements and the second semiconductor chip has a thickness of less than 100 μm,
- the second semiconductor chip has a second surface opposite to the first surface of the second semiconductor chip and a first electrically conductive layer is applied to the second surface of the second semiconductor chip,
- external contact pads are formed from the first electrically conductive layer,
- the first semiconductor chip extends beyond a periphery of the second semiconductor chip,
- a second electrically conductive layer is applied to at least one side surface of the second semiconductor chip and the second electrically conductive layer electrically couples at least one of the first connection elements to the first electrically conductive layer, and
- the at least one of the first connection elements is located outside of the periphery of the second semiconductor chip.
Dependencies are inferred from the claim text.